CY8C42123 Datasheet, PDF (1/42 Pages) Cypress Semiconductor – Power PSoC™ Devices

PRELIMINARY
CY8C42123/CY8C42223
CY8C42323/CY8C42423
Power PSoC™ Devices
1.0 Features
1.1 Key Features
• Extended Operating Voltage of 2.5V to 36V
• 2 HV Linear Opamp Control Loops for Driving Power PFETs
• 2 HV Switching Control Loops for Driving External PFETs
• 2 High Voltage CMOS or Open Drain Outputs
• 2 High Voltage Analog Sense Inputs
• 4KB of Flash
• 256 Bytes of SRAM
1.2 Improved Features
• Very Low Current Mode for 100 nA Sleep (Deep Sleep)
• Analog Absolute Accuracy (0.75%)
• Additional Flexibility for Sleep Modes
• 2 Comparators with DAC References
• 6- to 12-Bit ADC (20 Ksps at 8 Bits)
• Configurable Analog Mux, 10:1 or 5:2 Differential
• Configurable Digital Blocks
— 8- to 16-Bit Timers, Counters, and PWMs
— Connectable to All GPIO Pins
— Connectable to All High Voltage Output Pins
— Single Block Deadband PWM with Kill
— Digital Blocks can Drive Outputs to 36V
— Complex Peripherals by Combining Blocks
1.3 Applications
• Battery Chargers (Linear, Switched, or Fly Back)
• DC-DC Buck and Boost Converters
• Fan Controllers (Tachometer, Temp. Sense, Current Limit)
• Motor Drivers (H-Bridge, Hall-Effect Sensors)
• White LED Drivers
• Temperature Sensor (Thermistor, Thermocouple)
• General-Purpose High Voltage Microcontroller
2.0 Block Diagram
HVdd
GDO1
VS1
HVO[1]
P0[7]
P0[5]
P0[3]
P0[1]
P1[1]
PSoC CORE
SleepandWatchdog
POR andLVD
PSMo8CCCPOURE
4KBFlash
256BSRAM
SystemResets
InterruptController
LowDrop-Out
Regulator
DBC01
InternalVdd
ANALOG and HIGH VOLTAGE
SECTIONS
ODAC1
ODAC0
VDAC1
VBG
VDAC1 _IBIAS VDAC0
VDAC0
DBC00
HVDriver
Analog to
Digital
Convertor
HVDriver
IDAC1
Atten1
AMuxBus3
AMuxBus1
COMP1
ODAC1
Atten0
AMuxBus2
AMuxBus0
IDAC0
ODAC0
COMP0
Gl o bal Di gi tal In terco nnectBus
System Bus
DBC00 DBC01
DBD02
DigitalPSoC BlockArray
DIGITAL SYSTEM
DBD03
1DigitalRow
GDO0
VS0
HVO[0]
P0[6]
P0[4]
P0[2]
P0[0]
P1[0]
SYSTEM RESOURCES
LowSpeed
Oscillator
Internal
Voltag e
Reference
Internal
Main
Oscillator
I2C
Digital
Clocks
Cypress Semiconductor Corporation
Document 38-12034 Rev. *C
Figure 2-1. Block Diagram
• 198 Champion Court •
San Jose, CA 95134 • 408.943.2600
Revised November 17, 2005