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CY8C21234_12 Datasheet, PDF (1/50 Pages) Cypress Semiconductor – PSoC® Programmable System-on-Chip™ | |||
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CY8C21634, CY8C21534, CY8C21434
CY8C21334, CY8C21234
PSoC® Programmable System-on-Chipâ¢
PSoC® Programmable System-on-Chipâ¢
Features
â Powerful Harvard-architecture processor
â M8C processor speeds up to 24 MHz
â Low power at high speed
â Operating voltage: 2.4 V to 5.25 V
â Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
â Industrial temperature range: â40 °C to +85 °C
â Advanced peripherals (PSoC® blocks)
â Four analog Type E PSoC blocks provide:
⢠Two comparators with digital-to-analog converter (DAC)
references
⢠Single or dual 10-bit 28 channel analog-to-digital
converters (ADC)
â Four digital PSoC blocks provide:
⢠8- to 32-bit timers, counters, and pulse width modulators
(PWMs)
⢠Cyclical redundancy check (CRC) and pseudo random
sequence (PRS) modules
⢠Full-duplex universal asynchronous receiver transmitter
(UART), serial peripheral interface (SPI) master or slave
⢠Connectable to all general purpose I/O (GPIO) pins
â Complex peripherals by combining blocks
â Flexible on-chip memory
â 8 KB flash program storage 50,000 erase/write cycles
â 512 bytes static random access memory (SRAM) data
storage
â In-system serial programming (ISSP)
â Partial flash updates
â Flexible protection modes
â EEPROM emulation in flash
â Complete development tools
â Free development software (PSoC Designerâ¢)
â Full-featured, in-circuit emulator (ICE) and programmer
â Full-speed emulation
â Complex breakpoint structure
â 128-KB trace memory
â Precision, programmable clocking
â Internal ±2.5% 24- / 48-MHz main oscillator
â Internal oscillator for watchdog and sleep
â Programmable pin configurations
â 25-mA sink, 10-mA source on all GPIOs
â Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
â Up to eight analog inputs on GPIOs
â Configurable interrupt on all GPIOs
â Versatile analog mux
â Common internal analog bus
â Simultaneous connection of I/O combinations
â Capacitive sensing application capability
â Additional system resources
â I2C master, slave, and multi-master to 400 kHz
â Watchdog and sleep timers
â User-configurable low-voltage detection (LVD)
â Integrated supervisory circuit
â On-chip precision voltage reference
Logic Block Diagram
Cypress Semiconductor Corporation ⢠198 Champion Court
Document Number: 38-12025 Rev. *Y
⢠San Jose, CA 95134-1709 ⢠408-943-2600
Revised July 26, 2012
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