CY8C20X37 Datasheet, PDF (1/39 Pages) Cypress Semiconductor – 1.8 V CapSense® Controller with SmartSense™ Auto-tuning – 31 Buttons, 6 Sliders

CY8C20x37/37S/47/47S/67/67S
1.8 V CapSense^® Controller with
SmartSense™ Auto-tuning –
31 Buttons, 6 Sliders
1.8 V CapSense® Controller with SmartSense™ Auto-tuning Support
Features
■ QuietZone™ Controller
❐ Patented Capacitive Sigma Delta PLUS (CSD PLUS™)
sensing algorithm for robust performance
❐ High Sensitivity (0.1 pF) and best-in-class SNR performance
to support:
• Ideal for proximity solutions
• Overlay thickness of 15 mm for glass and 5 mm plastic
❐ Superior noise immunity performance against conducted and
radiated noise and ultra low radiated emissions
• Reliable and robust touch performance in noisy environ-
ments
❐ Standardized user modules for overcoming noise
■ Low power CapSense^® block with SmartSense™ auto-tuning
❐ Supports a combination of up to 31 buttons or 6 sliders, prox-
imity sensors
❐ Low average power consumption - 28 A for each sensor at
runtime (wake from sleep and scan sensors every 125 ms)
❐ SmartSense auto-tuning
• Sets and maintains optimal sensor performance during
runtime
• Eliminates system tuning during development and produc-
tion
• Compensates for variations in manufacturing process
■ Driven shield available on five GPIO pins
❐ Max load of 100 pF at 3 MHz
❐ Frequency range: 375 kHz to 3 MHz
❐ Delivers best-in class water tolerant designs
❐ Robust proximity sensing in the presence of metal objects
■ Powerful Harvard-architecture processor
❐ M8C CPU with a maximum speed of 24 MHz
❐ Operating range: 1.71 V to 5.5 V
• Standby mode: 1.1 µA (typ)
• Deep sleep: 0.1 µA (typ)
❐ Temperature range: –40 °C to +85 °C
■ Flexible on-chip memory
❐ 8 KB flash, 1 KB SRAM
❐ 16 KB flash, 2 KB SRAM
❐ 32 KB flash, 2 KB SRAM
❐ 50,000 flash erase/write cycles
❐ In-system programming capability
■ Four clock sources
❐ Internal main oscillator (IMO): 6/12/24 MHz
❐ Internal low-speed oscillator (ILO) at 32 kHz for watchdog
and sleep timers
❐ RC crystal oscillator
❐ Clock input
■ Programmable pin configurations
❐ Up to 32 general-purpose I/Os (GPIOs)
❐ Dual mode GPIO
❐ High sink current of 25 mA for each GPIO. Total 120 mA
maximum sink current per chip
❐ 5 mA source current on port 0 and 1 and 1 mA on port 2,3
and 4
❐ Configurable internal pull-up, high-Z, and open drain modes
❐ Selectable, regulated digital I/O on port 1
❐ Configurable input threshold on port 1
■ Versatile analog mux
❐ Common internal analog bus
❐ Simultaneous connection of I/O
❐ High power supply rejection ratio (PSRR) comparator
❐ Low-dropout voltage regulator for all analog resources
■ Additional system resources
❐ I²C slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• Selectable clock stretch or forced Nack mode
• Implementation during sleep modes with less than 100 µA
• I²C wake from sleep with hardware address validation
❐ 12 MHz SPI master and slave
❐ Three 16-bit timers
❐ Watchdog and sleep timers
❐ Internal voltage reference
❐ Integrated supervisory circuit
❐ 10-bit incremental analog-to-digital converter (ADC)
❐ Two general-purpose high speed, low power analog compar-
ators
■ Complete development tools
❐ Free development tool (PSoC Designer™)
■ Package options
❐ 16-pin SOIC (150 mil)
❐ 16-pin QFN – 3 × 3 × 0.6 mm
❐ 24-pin QFN – 4 × 4 × 0.6 mm
❐ 32-pin QFN – 5 × 5 × 0.6 mm
❐ 48-pin QFN – 6 × 6 × 0.6 mm
❐ 30-ball WLCSP^[1]
Note
1. Contact your nearest Cypress sales office for details.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-69257 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 3, 2012