|
CY8C20336H_12 Datasheet, PDF (1/35 Pages) Cypress Semiconductor – Haptics Enabled CapSense® Controller | |||
|
CY8C20336H, CY8C20446H
Haptics Enabled CapSense® Controller
Features
â 1.71-V to 5.5-V operating range
â Low power CapSense® block
â Configurable capacitive sensing elements
â Supports combination of CapSense buttons, sliders,
touchpads, touchscreens, and proximity sensors
â Powerful Harvard-architecture processor
â M8C CPU speed can be up to 24 MHz or sourced by an
external crystal, resonator, or clock signal
â Low power at high speed
â Interrupt controller
â Temperature range: â40 °C to +85 °C
â Flexible on-chip memory
â Two program/data storage size options:
⢠CY8C20336H: 8 KB flash / 1 KB SRAM
⢠CY8C20446H: 16 KB flash / 2 KB SRAM
â 50,000 flash erase/write cycles
â Partial flash updates
â Flexible protection modes
â In-System Serial Programming (ISSP)
â Precision, programmable clocking
â Internal main oscillator (IMO): 6/12/24 MHz ± 5%
â Internal low-speed oscillator (ILO) at 32 kHz for watchdog
and sleep timers
â Precision 32-kHz oscillator for optional external crystal
â Programmable pin configurations
â Up to 28 general-purpose I/Os (GPIOs) (depending on the
package)
â Dual-mode GPIO: All GPIOs support digital I/O and analog
inputs
â 25-mA sink current on each GPIO
⢠120-mA total sink current on all GPIOs
â Pull-up, high Z, open drain modes on all GPIOs
â CMOS drive mode: 5-mA source current on ports 0 and 1
and 1 mA on ports 2, 3, and 4
⢠20-mA total source current on all GPIOs
â Selectable, regulated digital I/O on port 1
â Configurable input threshold on port 1
â Hot swap capability on all port 1 GPIOs
â Integrates Immersion TS2000 Haptics technology for ERM
drive control
â Versatile analog mux
â Common internal analog bus
â Simultaneous connection of I/O
â High Power supply rejection ratio (PSRR) comparator
â Low dropout voltage regulator for all analog resources
â Additional system resources
â I2C slave:
⢠Selectable to 50 kHz, 100 kHz, or 400 kHz
⢠No clock stretching (under most conditions)
⢠Implementation during sleep modes with less than 100 µA
⢠Hardware address validation
â SPI master and slave: Configurable 46.9 kHz to 12 MHz
â Three 16-bit timers
â Watchdog and sleep timers
â Internal voltage reference
â Integrated supervisory circuit
â 8- to 10-bit incremental analog-to-digital converter (ADC)
â Two general-purpose high-speed, low-power analog
comparators
â Complete development tools
â Free development tool (PSoC Designerâ¢)
â Full featured, In-Circuit Emulator (ICE) and programmer
â Full-speed emulation
â Complex breakpoint structure
â 128 KB trace memory
â Package options
â CY8C20336H:
⢠24-pin 4 à 4 à 0.6 mm QFN
â CY8C20446H:
⢠32-pin 5 à 5 à 0.6 mm QFN
Cypress Semiconductor Corporation
⢠198 Champion Court
Document Number: 001-56223 Rev. *D
⢠San Jose, CA 95134-1709
â¢408-943-2600
Revised June 15, 2012
|
▷ |