CY7S1041G Datasheet, PDF (1/21 Pages) Cypress Semiconductor – 4-Mbit (256K words × 16 bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC)

CY7S1041G
CY7S1041GE
4-Mbit (256K words × 16 bit) Static RAM
with PowerSnooze™ and Error Correcting Code (ECC)
4-Mbit (256K words × 16 bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC)
Features
■ High speed
❐ Access time (t_AA) = 10 ns / 15 ns
■ Ultra-low power Deep-Sleep (DS) current
❐ I_DS = 15 µA
■ Low active and standby currents
❐ Active Current I_CC = 38-mA typical
❐ Standby Current I_SB2 = 6-mA typical
■ Wide operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V,
4.5 V to 5.5 V
■ Embedded ECC for single-bit error correction^[1]
■ 1.0-V data retention
■ TTL- compatible inputs and outputs
■ Error indication (ERR) pin to indicate 1-bit error detection and
correction
■ Available in Pb-free 44-pin TSOP II and 48-ball VFBGA
Functional Description
The CY7S1041G is a high-performance PowerSnooze^™ static
RAM organized as 256K words × 16 bits. This device features
fast access times (10 ns) and a unique ultra-low power
Deep-Sleep mode. With Deep-Sleep mode currents as low as
15 µA, the CY7S1041G/ CY7S1041GE devices combine the
best features of fast and low- power SRAMs in industry-standard
package options. The device also features embedded ECC. logic
which can detect and correct single-bit errors in the accessed
location.
Deep-Sleep input (DS) must be deasserted HIGH for normal
operating mode.
To perform data writes, assert the Chip Enable (CE) and Write
Enable (WE) inputs LOW, and provide the data and address on
device data pins (I/O₀ through I/O₁₅) and address pins (A₀
through A₁₇) respectively. The Byte High Enable (BHE) and Byte
Low Enable (BLE) inputs control byte writes, and write data on
the corresponding I/O lines to the memory location specified.
BHE controls I/O₈ through I/O₁₅ and BLE controls I/O₀ through
I/O₇.
To perform data reads, assert the Chip Enable (CE) and Output
Enable (OE) inputs LOW and provide the required address on
the address lines. Read data is accessible on the I/O lines (I/O₀
through I/O₁₅). You can perform byte accesses by asserting the
required byte enable signal (BHE or BLE) to read either the
upper byte or the lower byte of data from the specified address
location
The device is placed in a low-power Deep-Sleep mode when the
Deep-Sleep input (DS) is asserted LOW. In this state, the device
is disabled for normal operation and is placed in a low power data
retention mode. The device can be activated by deasserting the
Deep-Sleep input (DS) to HIGH.
The CY7S1041G is available in 44-pin TSOP II, 48-ball VFBGA
and 44-pin (400-mil) Molded SOJ.
Product Portfolio
Product ^[2]
Range
CY7S1041G(E)18
CY7S1041G(E)30
CY7S1041G(E)
Industrial
V_CC Range (V)
1.65 V–2.2 V
2.2 V–3.6 V
4.5–5.5 V
Speed
(ns)
15
10
10
Power Dissipation
Operating
(mA)
I_CC,
f = f_max
Typ ^[3] Max
Standby,
(mA)
I_SB2
Typ ^[3] Max
Deep-Sleep
current (µA)
Typ ^[3] Max
–
40
6
8
–
15
38
45
38
45
Notes
1. This device does not support automatic write back on error detection.
2. ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information for details.
3.
Typical values
V_CC = 3 V (for
are included for reference only and are
V_CC range of 2.2 V – 3.6 V), and V_CC =
not guaranteed or tested.
5 V (for V_CC range of 4.5
Typical
V – 5.5
values are measured
V), T_A = 25 °C.
at
V_CC
=
1.8
V
(for
V_CC
range
of
1.65
V
–
2.2
V),
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-92576 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 19, 2015