CY7C9915 Datasheet, PDF (1/14 Pages) Cypress Semiconductor – 3.3V Programmable Skew Clock Buffer

PRELIMINARY
CY7C9915
3.3V Programmable Skew Clock Buffer
Features
• All output pair skew <100 ps (typical)
• Input Frequency Range: 3.75 MHz to 150 MHz
• Output Frequency Range: 3.75 MHz to 150 MHz
• User-selectable output functions
— Selectable skew to 18 ns
— Inverted and non-inverted
— Operation at ¹â„₂ and ¹â„₄ input frequency
— Operation at 2x and 4x input frequency (input as low
as 3.75 MHz)
• Zero input-to-output delay
• 3.3V power supply
• ± 3.0% Output Duty Cycle Distortion
• LVTTL outputs drive 50Ω terminated lines
• Low operating current
• 32-pin PLCC package
• Jitter < 100ps peak-to-peak (< 15 ps RMS)
Block Diagram
TEST
FB
REF
PHASE
FREQ _FILTER
DET
VCO AND
TIME UNIT
GENERATOR
FS
4F0
4Q0
4F1
SELECT
4Q1
INPUTS
(THREE
LEVEL)
3F0
SKEW
3Q0
3F1
3Q1
SELECT
2Q0
2F0
2F1
MATRIX
2Q1
1F0
1Q0
1F1
1Q1
Functional Description
The CY7C9915 RoboClock is a 150-MHz Low-voltage
Programmable Skew Clock Buffer that offers user-selectable
control over system clock functions. This multiple-output clock
driver provides the system integrator with functions necessary
to optimize the timing of high-performance computer systems.
Eight individual drivers, arranged as four pairs of user-control-
lable outputs, can each drive terminated transmission lines
with impedances as low as 50Ω while delivering minimal and
specified output skews and full-swing logic levels (LVTTL).
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.42 to 1.6 ns are deter-
mined by the operating frequency with outputs able to skew up
to ±6 time units from their nominal “zero” skew position. The
completely integrated PLL allows external load and trans-
mission line delay effects to be canceled. When this “zero
delay” capability of the LVPSCB is combined with the
selectable output skew functions, the user can create
output-to-output delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility
minimizes clock distribution difficulty while allowing maximum
system clock speed and flexibility.
Pin Configuration
3F1
4F0
4F1
VCCQ
VCCN4
4Q1
4Q0
GND
GND
4 3 2 1 32 31 30
5
29
6
28
7
27
8
26
9 _{CY7C9915 25}
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
2F0
GND
1F1
1F0
VCCN1
1Q0
1Q1
GND
GND
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07687 Rev. *A
Revised April 29, 2005