CY7C9335A Datasheet, PDF (1/8 Pages) Cypress Semiconductor – SMPTE-259M/DVB-ASI Descrambler/Framer-Controller

CY7C9335A
SMPTE-259M/DVB-ASI
Descrambler/Framer-Controller
Features
• Fully compatible with SMPTE-259M
• Fully compatible with DVB-ASI
• Operates from a single +5V supply
• 100-pin TQFP package
• Decodes 10-bit parallel digital streams for 27M
characters/sec (270 Mbits/sec serial)
• Operates with CY7B9334 SMPTE HOTLink^ deseri-
alizer/receiver
• X⁹ + X⁴ + 1 descrambler and NRZI-to-NRZ decoder may
be bypassed for raw data output
Functional Description
SMPTE-259M Operation
The CY7C9335A is a CMOS integrated circuit designed to
decode SMPTE-125M bit-parallel digital characters (or other
data formats) using the SMPTE-259M decoding rules.
Following decoding, the characters are framed by locating the
30-bit TRS pattern in the parallel character stream. The
framed characters are then output.
The inputs of the CY7C9335A are designed to be directly
mated to a CY7B9334 HOTLink receiver, which converts the
SMPTE-259M compatible high-speed serial data stream into
10-bit parallel characters.
This device performs both TRS (sync) detection and framing,
data descrambling with the SMPTE-259M X⁹+X⁴+1 algorithm,
and NRZI-to-NRZ decoding. These functions operate at a 27
MHz character rate. For those systems operating with
non-SMPTE-259M compliant video streams (or for diagnostic
purposes), the descrambler and NRZI decoding functions can
be disabled.
DVB-ASI Operation
The CY7C9335A also contains the necessary multiplexers,
control inputs and outputs, to control a DVB-ASI-compliant
video stream. DVB-ASI operation is enabled through
activation of a single input signal. This allows a single
serial-to-parallel input port to support both SMPTE and DVB
data streams under software or hardware control.
In DVB-ASI mode the CY7C9335A automatically enables both
the 8B/10B decoder and multibyte framer present in the
CY7B9334 receiver/deserializer. All error detection, fill, and
command codes are detected and output by the CY7C9335A.
The CY7C9335A operates from a single +5V supply. It is
available in a 100-pin TQFP space saving package.
Logic Block Diagram
D₉(RVS)
D₈
D₇
D₆
D₅
D₄
D₃
D₂
D₁
D₀(SC/D)
SYNC_EN
BYPASS
DVB_EN
CKR
OE
19
10
10
10
11
10
4
RF
A/B
PD₉(SVS)
PD₈
PD₇
PD₆
PD₅
PD₄
PD₃
PD₂
PD₁
PD₀(SC/D)
H_SYNC
SYNC_ERR
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-02083 Rev. **
Revised October 13, 2003