CY7C68013A_06 Datasheet, PDF (1/60 Pages) Cypress Semiconductor – EZ-USB FX2LP™ USB Microcontroller

CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
EZ-USB FX2LP™ USB Microcontroller
1.0 Features (CY7C68013A/14A/15A/16A)
• USB 2.0–USB-IF high speed certified (TID # 40440111)
• Single-chip integrated USB 2.0 transceiver, smart SIE,
and enhanced 8051 microprocessor
• Fit, form and function compatible with the FX2
— Pin-compatible
— Object-code-compatible
— Functionally-compatible (FX2LP is a superset)
• Ultra Low power: I_CC no more than 85 mA in any mode
— Ideal for bus and battery powered applications
• Software: 8051 code runs from:
— Programmable waveform descriptors and configu-
ration registers to define waveforms
— Supports multiple Ready (RDY) inputs and Control
(CTL) outputs
• Integrated, industry-standard enhanced 8051
— 48-MHz, 24-MHz, or 12-MHz CPU operation
— Four clocks per instruction cycle
— Two USARTS
— Three counter/timers
— Expanded interrupt system
— Two data pointers
• 3.3V operation with 5V tolerant inputs
— Internal RAM, which is downloaded via USB
• Vectored USB interrupts and GPIF/FIFO interrupts
— Internal RAM, which is loaded from EEPROM
— External memory device (128 pin package)
• 16 KBytes of on-chip Code/Data RAM
• Separate data buffers for the Set-up and Data portions
of a CONTROL transfer
• Integrated I²C controller, runs at 100 or 400 kHz
• Four programmable BULK/INTERRUPT/ISOCHRO-
NOUS endpoints
— Buffering options: double, triple, and quad
• Additional programmable (BULK/INTERRUPT) 64-byte
endpoint
• 8- or 16-bit external data interface
• Smart Media Standard ECC generation
• GPIF (General Programmable Interface)
• Four integrated FIFOs
— Integrated glue logic and FIFOs lower system cost
— Automatic conversion to and from 16-bit buses
— Master or slave operation
— Uses external clock or asynchronous strobes
— Easy interface to ASIC and DSP ICs
• Available in Commercial and Industrial temperature
grade (all packages except VFBGA)
— Allows direct connection to most parallel interface
24 MHz
Ext. XTAL
FX2LP
High-performance micro
using standard tools
with lower-power options
/0.5
VCC ^x20 /1.0
PLL _/2.0
1.5k
connected for
full speed
D+
D–
Integrated
full- and high-speed
XCVR
USB
2.0
XCVR
CY
Smart
USB
1.1/2.0
Engine
8051 Core
12/24/48 MHz,
four clocks/cycle
16 KB
RAM
I²C
Master
Additional I/Os (24)
ECC
ADDR (9)
GPIF
RDY (6)
CTL (6)
4 kB
8/16
FIFO
Abundant I/O
including two USARTS
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
Up to 96 MBytes/s
burst rate
Enhanced USB core
Simplifies 8051 code
“Soft Configuration”
Easy firmware changes
FIFO and endpoint memory
(master or slave operation)
Figure 1-1. Block Diagram
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-08032 Rev. *K
Revised January 26, 2006
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