CY7C6431X_09_09 Datasheet, PDF (1/32 Pages) Cypress Semiconductor – enCoRe V Full Speed USB Controller

CY7C6431x
CY7C6434x, CY7C6435x
enCoRe™ V Full Speed USB Controller
Features
■ Powerful Harvard Architecture Processor
❐ M8C processor speeds running up to 24 MHz
❐ Low power at high processing speeds
❐ Interrupt controller
❐ 3.0V to 5.5V operating voltage without USB
❐ Operating voltage with USB enabled:
• 3.15V to 3.45V when supply voltage is around 3.3V
• 4.35V to 5.25V when supply voltage is around 5.0V
❐ Commercial temperature range: 0°C to +70°C
❐ Industrial temperature range: -40°C to +85°C
■ Flexible On-Chip Memory
❐ Up to 32K Flash program storage:
• 50,000 erase and write cycles
• Flexible protection modes
❐ Up to 2048 bytes SRAM data storage
❐ In-System Serial Programming (ISSP)
■ Complete Development Tools
❐ Free development tool (PSoC Designer™)
❐ Full featured, in-circuit emulator and programmer
❐ Full speed emulation
❐ Complex breakpoint structure
❐ 128K trace memory
■ Precision, Programmable Clocking
❐ Crystal-less oscillator with support for an external crystal or
resonator
❐ Internal ±5.0% 6, 12, or 24 MHz main oscillator:
• 0.25% accuracy with Oscillator Lock to USB data, no
external components required
• Internal low speed oscillator at 32 kHz for watchdog and
sleep. The frequency range is 19 to 50 kHz with a 32 kHz
typical value
■ Programmable Pin Configurations
❐ Up to 36 GPIO (Depending on Package)
❐ 25 mA sink current on all GPIO
❐ Pull Up, High Z, Open Drain, CMOS drive modes on all GPIO
❐ CMOS Drive Mode (5 mA Source Current) on Ports 0 and 1:
• 20 mA (at 3.0V) Total Source Current
❐ Low dropout voltage regulator for Port 1 pins:
• Programmable to output 3.0, 2.5, or 1.8V
❐ Selectable, regulated digital I/O on Port 1
❐ Configurable input threshold for Port 1
❐ Hot-swappable Capability on Port 1
■ Full-Speed USB (12 Mbps)
❐ Eight unidirectional endpoints
❐ One bidirectional control endpoint
❐ USB 2.0 compliant
❐ Dedicated 512 bytes buffer
❐ No external crystal required
■ Additional System Resources
❐ Configurable communication speeds
❐ I²C slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• Implementation requires no clock stretching
• Implementation during sleep modes with less than 100 μA
• Hardware address detection
❐ SPI master and SPI slave:
• Configurable between 46.9 kHz and 12 MHz
❐ Three 16-bit timers
❐ 10-bit ADC used to monitor battery voltage or other signals
with external components
❐ Watchdog and sleep timers
❐ Integrated supervisory circuit
enCoRe V Block Diagram
enCoRe V
CORE
SRAM
2048 Bytes
Interrupt
Controller
Port 4 Port 3 Port 2 Port 1 Port 0 Prog. LDO
SROM
8K/16K/32K Flash
CPU Core (M8C)
System Bus
Sleep and
Watchdog
6/12/24 MHz Internal Main Oscillator
ADC
3 16-Bit
Timers
I2C Slave/SPI
Master-Slave
POR and LVD
System Resets
Full
Speed
USB
SYSTEM RESOURCES
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-12394 Rev *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 15, 2009
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