CY7C604XX_13 Datasheet, PDF (1/38 Pages) Cypress Semiconductor – enCoRe™ V Low Voltage Microcontroller

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CY7C604XX
enCoRe™ V Low Voltage Microcontroller
Features
■ Powerful Harvard Architecture processor
❐ M8C processor speeds running up to 24 MHz
❐ Low power at high processing speeds
❐ Interrupt controller
❐ 1.71 V to 3.6 V operating voltage
❐ Commercial temperature range: 0 °C to +70 °C
■ Flexible on-chip memory
❐ Up to 32 K flash program storage
• 50,000 erase and write cycles
• Flexible protection modes
❐ Up to 2048 bytes SRAM data storage
❐ In-system serial programming (ISSP)
■ Complete development tools
❐ Free development tool (PSoC^® Designer™)
❐ Full-featured, in-circuit emulator and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 K trace memory
■ Precision, programmable clocking
❐ Crystal-less oscillator with support for an external crystal or
resonator
❐ Internal ±5.0% 6, 12, or 24 MHz main oscillator
❐ Internal low-speed oscillator at 32 kHz for watchdog and
sleep. The frequency range is 19 to 50 kHz with a 32 kHz
typical value
enCoRe V LV Block Diagram
■ Programmable pin configurations
❐ Up to 36 GPIO (depending on package)
❐ 25 mA sink current on all GPIO
❐ Pull-up, High Z, open drain, CMOS drive modes on all GPIO
❐ CMOS drive mode (5 mA source current) on Ports 0 and 1:
• 20 mA (at 3.0 V) total source current
❐ Low dropout voltage regulator for Port 1 pins:
• Programmable to output 3.0, 2.5, or 1.8V
❐ Selectable, regulated digital I/O on Port 1
❐ Configurable input threshold for Port 1
❐ Hot-swappable capability on Port 1
■ Additional system resources
❐ Configurable communication speeds
❐ I²C Slave
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• Implementation requires no clock stretching
• Implementation during sleep modes with less than 100 mA
• Hardware address detection
❐ SPI master and SPI slave
• Configurable between 46.9 kHz and 12 MHz
❐ Three 16-bit timers
❐ 10-bit ADC used to monitor battery voltage or other signals
with external components
❐ Watchdog and sleep timers
❐ Integrated supervisory circuit
enCoRe V
CORE
SRAM
2048 Bytes
Interrupt
Controller
Port 4 Port 3 Port 2 Port 1 Port 0 Prog. LDO
SROM
8 K / 16 K / 32 K
Flash
CPU Core (M8C)
System Bus
Sleep and
Watchdog
6 / 12 / 24 MHz Internal Main Oscillator
ADC
3 16-Bit
Timers
I2C Slave/SPI
Master-Slave
POR and LVD
System Resets
System Resources
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-12395 Rev. *N
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 24, 2013