CY7C53150 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – Neuron Chip Network Processor

CY7C53150
CY7C53120
Neuron^® Chip Network Processor
Features
• Three eight-bit pipelined processors for concurrent
processing of application code and network traffic
• 11-pin I/O port programmable in 34 modes for fast appli-
cation program development
• Two 16-bit timer/counters for measuring and gener-
ating I/O device waveforms
• Five-pin communication port that supports direct
connect and network transceiver interfaces
• Programmable pull-ups on IO4–IO7 and 20-mA sink
current on IO0–IO3
• Unique 48-bit ID number in every device to facilitate
network installation and management
• Low operating current; sleep mode operation for
reduced current consumption^[1]
• 0.35-µm Flash process technology
• 5.0V operation
• On-chip LVD circuit to prevent nonvolatile memory
corruption during voltage drops
• 2,048 bytes of SRAM for buffering network data,
system, and application data storage
• 512 bytes (CY7C53150), 2048 bytes (CY7C53120E2),
4096 bytes (CY7C53120E4) of Flash memory with
on-chip charge pump for flexible storage of configu-
ration data and application code
• Addresses up to 58 KB of external memory
(CY7C53150)
• 10 KB (CY7C53120E2), 12 KB (CY7C53120E4) of ROM
containing LonTalk^ network protocol firmware
• Maximum input clock operation of 20 MHz
(CY7C53150), 10 MHz (CY7C53120E2), 40 MHz
(CY7C53120E4) over a –40°C to 85°C^[2] temperature
range
• 64-pin TQFP package (CY7C53150)
• 32-pin SOIC or 44-pin TQFP package (CY7C53120)
Logic Block Diagram
Media Access
Control Processor
Functional Description
The CY7C531x0 Neuron^ chip implements a node for
LonWorks^ distributed intelligent control networks. It incorpo-
rates, on a single chip, the necessary communication and
control functions, both in hardware and firmware, that facilitate
the design of a LonWorks node.
The CY7C531x0 contains a very flexible five-pin communi-
cation port that can be configured to interface with a wide
variety of media transceivers at a wide range of data rates. The
most common transceiver types are twisted-pair, powerline,
RF, IR, fiber-optics, and coaxial.
The CY7C531x0 is manufactured using state-of-the-art
0.35-µm Flash technology, providing to designers the most
cost-effective Neuron chip solution.
Services at every layer of the OSI networking reference model
are implemented in the LonTalk firmware-based protocol
stored in 10-KB ROM (CY7C53120E2), 12-KB ROM
(CY7C53120E4), or off-chip memory (CY7C53150). The
firmware also contains 34 preprogrammed I/O drivers, greatly
simplifying application programming. The application program
is stored in the Flash memory (CY7C53120) and/or off-chip
memory (CY7C53150), and may be updated by downloading
over the network.
The CY7C53150 incorporates an external memory interface
that can address up to 64 KB with 6 KB of the address space
mapped internally. LonWorks nodes that require large appli-
cation programs can take advantage of this external memory
capability.
The CY7C53150 Neuron chip is an exact replacement for the
Motorola MC143150Bx and Toshiba TMPN3150B1 devices.
The CY7C53120E2 Neuron chip is an exact replacement for
the Motorola MC143120E2 device since it contains the same
firmware in ROM.
Communications
CP4
Port
CP0
Network
Processor
Application
Processor
2 KB RAM
Flash
Internal
Data Bus
(0:7)
Internal
Address Bus
(0:15)
I/O Block
2 Timer/
Counters
Oscillator,
Clock, and
Control
IO10
IO0
CLK1
CLK2
SERVICE
RESET
ROM
(CY7C53120)
External
Address/Data Bus
(CY7C53150)
Notes:
1. Rare combinations of wake-up events occurring during the go to sleep sequence could produce unexpected sleep behavior. For details please refer to Cypress’s
Neuron Metastability Description application note.
2. Maximum Junction Temperature is 105°C. T_Junction = T_Ambient + V•I•θ_JA. 32-pin SOIC θ_JA = 51C/W. 44-pin TQFP θ_JA = 43C/W. 64-pin TQFP θ_JA = 44C/W.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-10001 Rev. *D
Revised March 24, 2003