CY7C470 Datasheet, PDF (1/15 Pages) Cypress Semiconductor – 8K x 9 FIFO, 16K x 9 FIFO 32K x 9 FIFO with Programmable Flags

1CY 7C47 4
CY7C470
CY7C472
CY7C474
8K x 9 FIFO, 16K x 9 FIFO
32K x 9 FIFO with Programmable Flags
Features
• 8K x 9, 16K x 9, and 32K x 9 FIFO buffer memory
• Asynchronous read/write
• High-speed 33.3-MHz read/write independent of
depth/width
• Low operating power
— I_CC (max.) = 70 mA
• Programmable Almost Full/Empty flag
• Empty, Almost Empty, Half Full, Almost Full, and Full
status flags
• Programmable retransmit
• Expandable in width
• 5V ± 10% supply
• TTL compatible
• Three-state outputs
• Proprietary 0.8-micron CMOS technology
Functional Description
The CYC47X FIFO series consists of high-speed, low-power,
first-in first-out (FIFO) memories with programmable flags and
retransmit mark. The CY7C470, CY7C472, and CY7C474 are
8K, 16K, and 32K words by 9 bits wide, respectively. They are
offered in 600-mil DIP, PLCC, and LCC packages. Each FIFO
memory is organized such that the data is read in the same
sequential order that it was written. Three status pins—Emp-
ty/Full (E/F), Programmable Almost Full/Empty (PAFE), and
Half Full (HF)—are provided to the user. These pins are de-
coded to determine one of six states: Empty, Almost Empty,
Less than Half Full, Greater than Half Full, Almost Full, and
Full.
The read and write operations may be asynchronous; each
can occur at a rate of 33.3 MHz. The write operation occurs
when the write (W) signal goes LOW. Read occurs when read
(R) goes LOW. The nine data outputs go into a high-imped-
ance state when R is HIGH.
The user can store the value of the read pointer for retransmit
by using the MARK pin. A LOW on the retransmit (RT) input
causes the FIFO to resend data by resetting the read pointer
to the value stored in the mark pointer.
In the standalone and width expansion configurations, a LOW
on the retransmit (RT) input causes the FIFO to resend the
data. With the mark feature, retransmit can start from any word
in the FIFO.
The CYC47X series is fabricated using a proprietary 0.8-mi-
cron N-well CMOS technology. Input ESD protection is greater
than 2001V and latch-up is prevented by the use of reliable
layout techniques, guard rings, and a substrate bias generator.
Logic Block Diagram
DATAINPUTS
(D₀–D₈)
PROGRAMMABLE
FLAG REGISTER
WRITE
W
POINTER
RAM ARRAY
8K x 9
16K x 9
32K x 9
FLAG
LOGIC
READ
POINTER
THREE–
STATE
BUFFERS
DATAOUTPUTS
(Q₀–Q₈ )
MARK
POINTER
RESET
LOGIC
HF
E/F
PAFE
R
RT
MARK
Pin Configurations
PLCC/LCC
Top View
4 3 2 1 32 31 30
D₂ ⁵
6
D₁
7
D₀
MARK ⁸
7C470
29 D6
28 D7
27 ^NC
26 RT
PAFE ⁹
Q₀ ¹⁰
7C472
7C474
25 MR
24 E/F
Q₁ ¹¹
NC ¹²
23 _HF
22 ^Q7
Q₂
13
21
14 15 16 17 18 19 20
Q₆
7C470–2
DIP
Top View
W1
28 ^Vcc
D₈ 2
27 D4
D₃ 3
26 D5
D₂ 4
25 ^D6
D₁ 5
24 D7
D_{0 6 7C470 23 RT}
MARK
7
7C472
7C474
22
MR
PAFE ₈
21 E/F
Q_{0 9}
20 HF
Q_{1 10}
19 Q7
Q₂ 11
Q_{3 12}
Q_{8 13}
18 ^Q6
17 ^Q5
16 ^Q4
GND 14
15 R
7C470–3
MR
7C470–1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 1990 – Revised April 1995