CY7C460A Datasheet, PDF (1/15 Pages) Cypress Semiconductor – Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs

60A
CY7C460A/CY7C462A
CY7C464A/CY7C466A
Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs
Features
Functional Description
• High-speed, low-power, first-in first-out (FIFO)
memories
• 8K x 9 FIFO (CY7C460A)
• 16K x 9 FIFO (CY7C462A)
• 32K x 9 FIFO (CY7C464A)
• 64K x 9 FIFO (CY7C466A)
• 10-ns access times, 20-ns read/write cycle times
• High-speed 50-MHz read/write independent of
depth/width
• Low operating power
— I_CC= 60 mA
— I_SB =8 mA
• Asynchronous read/write
• Empty and Full flags
• Half Full flag (in standalone mode)
• Retransmit (in standalone mode)
• TTL-compatible
• Width and Depth Expansion Capability
• 5V ± 10% supply
• PLCC, LCC, 300-mil and 600-mil DIP packaging
• Three-state outputs
• Pin compatible density upgrade to CY7C42X/46X family
• Pin compatible and functionally equivalent to IDT7205,
IDT7206, IDT7207, IDT7208
The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are
respectively, 8K, 16K, 32K, and 64K words by 9-bit wide first-in
first-out (FIFO) memories. Each FIFO memory is organized
such that the data is read in the same sequential order that it
was written. Full and Empty flags are provided to prevent over-
run and underrun. Three additional pins are also provided to
facilitate unlimited expansion in width, depth, or both. The
depth expansion technique steers the control signals from one
device to another by passing tokens.
The read and write operations may be asynchronous; each
can occur at a rate of up to 50 MHz. The write operation occurs
when the Write (W) signal is LOW. Read occurs when Read
(R) goes LOW. The nine data outputs go to the high-imped-
ance state when R is HIGH.
A Half Full (HF) output flag is provided that is valid in the stan-
dalone (single device) and width expansion configurations. In
the depth expansion configuration, this pin provides the ex-
pansion out (XO) information that is used to tell the next FIFO
that it will be activated.
In the standalone and width expansion configurations, a LOW
on the Retransmit (RT) input causes the FIFOs to retransmit
the data. Read Enable (R) and Write Enable (W) must both be
HIGH during a retransmit cycle, and then R is used to access
the data.
The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are
fabricated using Cypress’s advanced 0.5µ RAM3 CMOS tech-
nology. Input ESD protection is greater than 2000V and
latch-up is prevented by careful layout and the use of guard
rings.
Logic Block Diagram
DATA INPUTS
(D₀−D ₈)
W
WRITE
CONTROL
WRITE
POINTER
DUAL PORT
RAM ARRAY
8K x 9
16K x 9
32K x 9
64K x 9
R
READ
CONTROL
THREE–
STATE
BUFFERS
DATA OUTPUTS
(Q₀-Q ₈)
READ
POINTER
RESET
LOGIC
Pin Configurations
PLCC/LCC
Top View
D₂
D₁
D₀
XI
FF
Q₀
Q₁
NC
Q₂
MR
FL/RT
W
4 3 2 1 32 31 30
D₈
5
29 D6
D₃
6
28 D7
D₂
7
27 ^NC
D₁
8
7C460A
7C462A
26 FL/RT
D₀
9
7C464A
25 MR
XI
10
7C466A
24 EF
FF
11
23 XO/HF Q₀
12
22 ^Q7
Q₁
13
21 Q6
14 15 16 17 18 19 20
Q₂
Q₃
Q₈
C46XA–2
GND
DIP
Top View
1
28
2
27
3
26
4
25
5
24
6
7C460A
7C462A
23
7 7C464A 22
8 ^7C466A 21
9
20
10
19
11
18
12
17
13
16
14
15
V_CC
D₄
D₅
D₆
D₇
FL/RT
MR
EF
XO/HF
Q₇
Q₆
Q₅
Q₄
R
C46XA–3
FLAG
LOGIC
EF
FF
EXPANSION
XI
LOGIC
XO/HF
C46XA–1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06011 Rev. *A
Revised December 26, 2002