CY7C4421_05 Datasheet, PDF (1/19 Pages) Cypress Semiconductor – 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

CY7C4421/4201/4211/4221 CY7C4231/4241/425164/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Features
• Pb-Free Packages Available
• High-speed, low-power, First-In, First-Out (FIFO)
memories
— 64 × 9 (CY7C4421)
— 256 × 9 (CY7C4201)
— 512 × 9 (CY7C4211)
— 1K × 9 (CY7C4221)
— 2K × 9 (CY7C4231)
— 4K × 9 (CY7C4241)
— 8K × 9 (CY7C4251)
• High-speed 100-MHz operation (10 ns Read/Write cycle
time)
• Low power (I_CC = 35 mA)
• Fully asynchronous and simultaneous Read and Write
operation
• Empty, Full, and Programmable Almost Empty and
Almost Full status flags
• TTL-compatible
• Expandable in width
• Output Enable (OE) pin
• Independent Read and Write enable pins
• Center power and ground pins for reduced noise
• Width-expansion capability
• Space saving 7 mm × 7 mm 32-pin TQFP
• Pin-compatible and functionally equivalent to
IDT72421, 72201, 72211, 72221, 72231, and 72241
Logic Block Diagram ^{D0- 8}
INPUT
REGISTER
Functional Description
The CY7C42X1 are high-speed, low-power FIFO memories
with clocked Read and Write interfaces. All are 9 bits wide. The
CY7C42X1 are pin-compatible to IDT722X1. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor inter-
faces, and communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
Write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running Read clock (RCLK) and two
Read-enable pins (REN1, REN2). In addition, the CY7C42X1
has an output enable pin (OE). The Read (RCLK) and Write
(WCLK) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
Read/Write applications. Clock frequencies up to 100 MHz are
achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data.
Pin Configurations
PLCC
Top View
WCLK WEN1 WEN2/LD
Write
CONTROL
Write
POINTER
RS
RESET
LOGIC
Dual Port
RAM Array
64 x 9
8k x 9
THREE-STATE
OUTPUT REGISTER
OE
FLAG
PROGRAM
REGISTER
FLAG
LOGIC
Read
POINTER
EF
PAE
PAF
FF
Read
CONTROL
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
OE
4 3 2 1 32 3130
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
141516 171819 20
RS
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
TQFP
Top View
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
Q0 _{- 8}
RCLK REN1 REN2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-06016 Rev. *C
Revised August 2, 2005