CY7C4285V-15ASXI Datasheet, PDF (1/24 Pages) Cypress Semiconductor – 8 K/16 K/32 K/64 K x 18 Low Voltage Deep Sync FIFOs

CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
8 K/16 K/32 K/64 K × 18 Low Voltage
Deep Sync FIFOs
32 K/64 K × 18 Low Voltage Deep Sync FIFOs
Features
■ 3.3 V operation for low power consumption and easy integration
into low voltage systems
■ High speed, low power, first-in first-out (FIFO) memories
■ 8 K × 18 (CY7C4255V)
■ 16 K × 18 (CY7C4265V)
■ 32 K × 18 (CY7C4275V)
■ 64 K × 18 (CY7C4285V)
■ 0.35 micron CMOS for optimum speed and power
■ High speed 100 MHz operation (10 ns read/write cycle times)
■ Low power
❐ I_CC = 30 mA
❐ I_SB = 4 mA
■ Fully asynchronous and simultaneous read and write operation
■ Empty, Full, Half Full, and programmable Almost Empty and
Almost Full status flags
■ Retransmit function
■ Output Enable (OE) pin
■ Independent read and write enable pins
■ Supports free running 50% duty cycle clock inputs
■ Width Expansion Capability
■ Depth Expansion Capability
■ 64-pin 10×10 STQFP
■ Pin compatible density upgrade to CY7C42X5V-ASC families
■ Pin compatible 3.3 V solutions for CY7C4255/65/75/85V
Selection Guide
Parameter
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Setup (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply Current (I_CC1) (mA)
Commercial
Industrial
Functional Description
The CY7C4255/65/75/85V are high speed, low power, first-in
first-out (FIFO) memories with clocked read and write interfaces.
All are 18 bits wide and are pin and functionally compatible to the
CY7C42X5V Synchronous FIFO family. The
CY7C4255/65/75/85V can be cascaded to increase FIFO depth.
Programmable features include Almost Full/Almost Empty flags.
These FIFOs provide solutions for a wide variety of data
buffering needs, including high speed data acquisition,
multiprocessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and a write enable
pin (WEN).
When WEN is asserted, data is written into the FIFO on the rising
edge of the WCLK signal. While WEN is held active, data is
continually written into the FIFO on each cycle. The output port
is controlled in a similar manner by a free-running read clock
(RCLK) and a read enable pin (REN). In addition, the
CY7C4255/65/75/85V have an output enable pin (OE). The read
and write clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read or write applications. Clock frequencies up to 67 MHz are
achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI, RXI),
cascade output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of
the next device, and the WXO and RXO pins of the last device
must be connected to the WXI and RXI pins of the first device.
The FL pin of the first device is tied to VSS and the FL pin of all
the remaining devices must be tied to VCC .
7C4255/65/75/85V-10
100
8
10
3.5
0
8
30
7C4255/65/75/85V-15
66.7
10
15
4
0
10
30
35
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06012 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 31, 2010
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