CY7C4275 Datasheet, PDF (1/21 Pages) Cypress Semiconductor – 32K/64Kx18 Deep Sync FIFOs

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CY7C4275
CY7C4285
32K/64Kx18 Deep Sync FIFOs
Features
Functional Description
• High-speed, low-power, first-in first-out (FIFO)
memories
• 32K x 18 (CY7C4275)
• 64K x 18 (CY7C4285)
• 0.5 micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
times)
• Low power
— I_CC=50 mA
— I_SB = 2 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
• TTL compatible
• Retransmit function
• Output Enable (OE) pin
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• 68-pin PLCC and 64-pin 10x10 TQFP
• Pin-compatible density upgrade to CY7C42X5
families
• Pin-compatible density upgrade to
IDT72205/15/25/35/45
The CY7C4275/85 are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 18 bits wide and are pin/functionally compatible to the
CY7C42X5 Synchronous FIFO family. The CY7C4275/85 can
be cascaded to increase FIFO depth. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and commu-
nications buffering.
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and a write enable
pin (WEN).
When WEN is asserted, data is written into the FIFO on the rising
edge of the WCLK signal. While WEN is held active, data is continu-
ally written into the FIFO on each cycle. The output port is controlled
in a similar manner by a free-running read clock (RCLK) and a read
enable pin (REN). In addition, the CY7C4275/85 have an output
enable pin (OE). The read and write clocks may be tied together for
single-clock operation or the two clocks may be run independently for
asynchronous read/write applications. Clock frequencies up to 100
MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI,
RXI), cascade output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of the
next device, and the WXO and RXO pins of the last device should be
connected to the WXI and RXI pins of the first device. The FL pin of
the first device is tied to V_SS and the FL pin of all the remaining devic-
es should be tied to V_CC.
D_{0 –17}
Logic Block Diagram
INPUT
REGISTER
WCLK
WEN
WRITE
CONTROL
WRITE
POINTER
RAM
ARRAY
32Kx18
64Kx18
FLAG
PROGRAM
REGISTER
FLAG
LOGIC
READ
POINTER
FF
EF
PAE
PAF
SMODE
RS
RESET
LOGIC
FL/RT
WXI
WXO/HF
RXI
RXO
EXPANSION
LOGIC
THREE–STATE
OUTPUT REGISTER
Q_{0– 17}
OE
READ
CONTROL
RCLK REN 4275–1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06008 Rev. *A
Revised December 26, 2002