CY7C4261V_11 Datasheet, PDF (1/22 Pages) Cypress Semiconductor – 16 K / 32 K / 64 K / 128 K x 9 Low-Voltage Deep Sync FIFOs

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CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
16 K / 32 K / 64 K / 128 K × 9
Low-Voltage Deep Sync™ FIFOs
Features
■ 3.3 V operation for low-power consumption and easy
integration into low-voltage systems
■ High-speed, low-power, first-in first-out (FIFO) memories
■ 16 K × 9 (CY7C4261V)
■ 32 K × 9 (CY7C4271V)
■ 64 K × 9 (CY7C4281V)
■ 128 K × 9 (CY7C4291V)
■ 0.35-micron CMOS for optimum speed or power
■ High-speed 100-MHz operation (10-ns read/write cycle
times)
■ Low power
❐ I_CC = 25 mA
❐ I_SB = 4 mA
■ Fully asynchronous and simultaneous read and write
operation
■ Empty, Full, and programmable Almost Empty and Almost
Full status flags
■ Output-enable (OE) pin
■ Independent read- and write-enable pins
■ Supports free-running 50% duty cycle clock inputs
■ Width-expansion capability
■ Pin-compatible 3.3 V solutions for CY7C4261/71/81/91
■ Pin-compatible density upgrade to CY7C42X1V family
■ Pb-free packages available
Functional Description
The CY7C4261/71/81/91V are high-speed, low-power FIFO
memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4261/71/81/91V are pin-compatible to the
CY7C42x1V Synchronous FIFO family. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
Selection Guide
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor
interfaces, and communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1 and WEN2/LD are held active, data is continually
written into the FIFO on each WCLK cycle. The output port is
controlled in a similar manner by a free-running read clock
(RCLK) and two read-enable pins (REN1, REN2). In addition,
the CY7C4261/71/81/91V has an output-enable pin (OE). The
read (RCLK) and write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run
independently for asynchronous read/write applications. Clock
frequencies up to 100 MHz are achievable. Depth expansion
is possible using one enable input for system control, while the
other enable is controlled by expansion logic to direct the flow
of data.
The CY7C4261/71/81/91V provides four status pins: Empty,
Full, Programmable Almost Empty, and Programmable Almost
Full. The Almost Empty/Almost Full flags are programmable to
single word granularity. The programmable flags default to
Empty +7 and Full –7.
The flags are synchronous, that is, they change state relative
to either the read clock (RCLK) or the write clock (WCLK).
When entering or exiting the Empty and Almost Empty states,
the flags are updated exclusively by the RCLK. The flags
denoting Almost Full, and Full states are updated exclusively
by WCLK. The synchronous flag architecture guarantees that
the flags maintain their status for at least one cycle.
All configurations are fabricated using an advanced 0.35 
CMOS technology. Input ESD protection is greater than 2001
V, and latch-up is prevented by the use of guard rings.
Maximum frequency
Maximum access time
Minimum cycle time
Minimum data or enable setup
Minimum data or enable hold
Maximum flag delay
Active power supply
current (I_CC1)
Commercial
Industrial
7C4261/71/81/91V-10
100
8
10
3.5
0
8
25
–
7C4261/71/81/91V-15
66.7
10
15
4
0
10
25
30
7C4261/71/81/91V-25
40
15
25
6
1
15
25
–
Unit
MHz
ns
ns
ns
ns
ns
mA
Density
Package
CY7C4261V
16 K x 9
32-pin PLCC
CY7C4271V
32 K x 9
32-pin PLCC
CY7C4281V
64 K x 9
32-pin PLCC
CY7C4291V
128 K x 9
32-pin PLCC
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-06013 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 30, 2011
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