CY7C4255_09 Datasheet, PDF (1/23 Pages) Cypress Semiconductor – 8K/16K x 18 Deep Sync FIFOs

CY7C4255, CY7C4265, CY7C4265A
8K/16K x 18 Deep Sync FIFOs
Features
Functional Description
■ High Speed, Low Power, First-In First-Out (FIFO) Memories
❐ 8K x 18 (CY7C4255)
❐ 16K x 18 (CY7C4265/4265A)^[1]
■ 0.5 Micron CMOS for Optimum Speed and Power
■ High Speed 100 MHz Operation (10 ns read/write cycle times)
■ Low Power — I_CC = 45 mA
■ Fully Asynchronous and Simultaneous Read and Write
Operation
■ Empty, Full, Half Full, and Programmable Almost Empty and
Almost Full Status Flags
■ TTL compatible
■ Retransmit Function
■ Output Enable (OE) Pins
■ Independent Read and Write Enable Pins
■ Center Power and Ground Pins for Reduced Noise
■ Supports Free-running 50 percent Duty Cycle Clock Inputs
■ Width and Depth Expansion Capability
■ 64-pin TQFP and 64-pin STQFP
■ Pin-compatible Density Upgrade to CY7C42X5 Family
■ Pin-compatible Density Upgrade to IDT72205/15/25/35/45
■ Pb-free Packages Available
Logic Block Diagram
The CY7C4255/65/65A are high speed, low power, first-in
first-out (FIFO) memories with clocked read and write interfaces.
All are 18 bits wide and are pin/functionally compatible to the
CY7C42X5 Synchronous FIFO family. The CY7C4255/65/65A
can be cascaded to increase FIFO depth. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs, including
high speed data acquisition, multiprocessor interfaces, and communi-
cations buffering.
These FIFOs have 18-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free running Clock (WCLK) and a Write Enable
pin (WEN). When WEN is asserted, data is written into the FIFO on the
rising edge of the WCLK signal. While WEN is held active, data is contin-
ually written into the FIFO on each cycle. The output port is controlled in
a similar manner by a free-running Read Clock (RCLK) and a Read
Enable pin (REN). In addition, the CY7C4255/65/65A have an Output
Enable pin (OE). The read and write clocks may be tied together for
single-clock operation or the two clocks may be run independently for
asynchronous read/write applications. Clock frequencies up to
100 MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices. Depth expansion is
possible using the Cascade Input (WXI, RXI), Cascade Output
(WXO, RXO), and First Load (FL) pins. The WXO and RXO pins are
connected to the WXI and RXI pins of the next device, and the WXO
and RXO pins of the last device should be connected to the WXI and
RXI pins of the first device. The FL pin of the first device is tied to V_SS
and the FL pin of all the remaining devices should be tied to V_CC.
D_0–17
INPUT
REGISTER
WCLK
WEN
WRITE
CONTROL
WRITE
POINTER
RS
RESET
LOGIC
FL/RT
WXI
WXO/HF
RXI
RXO
EXPANSION
LOGIC
Note
1. CY7C4265 and CY7C4265A are functionally identical
RAM
ARRAY
8K x 18
16K x 18
FLAG
PROGRAM
REGISTER
FLAG
LOGIC
READ
POINTER
FF
EF
PAE
PAF
SMODE
THREE–STATE
OUTPUT REGISTER
Q_0–17
OE
READ
CONTROL
RCLK
REN
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-06004 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 03, 2009
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