CY7C4205_11 Datasheet, PDF (1/25 Pages) Cypress Semiconductor – 256/512/1K/4K x 18 Synchronous FIFOs

CY7C4205/CY7C4215
CY7C4225/CY7C4245
256/512/1K/4K x 18 Synchronous FIFOs
Features
■ High speed, low power, first-in first-out (FIFO) memories
■ 256 x 18 (CY7C4205)
■ 512 x 18 (CY7C4215)
■ 1K x 18 (CY7C4225)
■ 4K x 18 (CY7C4245)
■ High speed 100 MHz operation (10 ns read/write cycle time)
■ Low power (I_CC = 45 mA)
■ Fully asynchronous and simultaneous read and write operation
■ Empty, full, half full, and programmable almost empty/almost
Full status flags
■ Transistor-transistor logic (TTL) compatible
■ Retransmit function
■ Output enable (OE) pin
■ Independent read and write enable pins
■ Center power and ground for reduced noise
■ Supports free running 50% duty cycle clock inputs
■ Width expansion capability
■ Depth expansion capability
■ Available in 64 pin 14 x 14 thin quad flat package (TQFP) and
64 pin 10 x 10 TQFP
Functional Description
The CY7C42X5 are high speed, low power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All are
18 bits wide and are pin/functionally compatible to IDT722X5.
The CY7C42X5 can be cascaded to increase FIFO depth.
Programmable features include Almost Full/Almost Empty flags.
These FIFOs provide solutions for a wide variety of data
buffering needs, including high speed data acquisition, multipro-
cessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and a write enable
pin (WEN). When WEN is asserted, data is written into the FIFO
on the rising edge of the WCLK signal. While WEN is held active,
data is continually written into the FIFO on each cycle. The
output port is controlled in a similar manner by a free-running
read clock (RCLK) and a read enable pin (REN). In addition, the
CY7C42X5 have an output enable pin (OE). The read and write
clocks may be tied together for single-clock operation or the two
clocks may be run independently for asynchronous read/write
applications. Clock frequencies up to 100 MHz are achievable.
Retransmit and synchronous almost full/almost empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI, RXI),
cascade output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of
the next device, and the WXO and RXO pins of the last device
should be connected to the WXI and RXI pins of the first device.
The FL pin of the first device is tied to VSS and the FL pin of all
the remaining devices should be tied to VCC.
The CY7C42X5 provides five status pins. These pins are
decoded to determine one of five states: Empty, Almost Empty,
Half Full, Almost Full, and Full (see Table 2). The Half Full flag
shares the WXO pin. This flag is valid in the standalone and
width-expansion configurations. In the depth expansion, this pin
provides the expansion out (WXO) information that is used to
signal the next FIFO when it will be activated.
The Empty and Full flags are synchronous, i.e., they change
state relative to either the read clock (RCLK) or the write clock
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag archi-
tecture guarantees that the flags will remain valid from one clock
cycle to the next. As mentioned previously, the Almost
Empty/Almost Full flags become synchronous if the
VCC/SMODE is tied to VSS. All configurations are fabricated
using an advanced 0.65m N-Well CMOS technology. Input ESD
protection is greater than 2001V, and latch-up is prevented by
the use of guard rings.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-45652 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 25, 2011
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