CY7C408A-409A Datasheet, PDF (1/16 Pages) Cypress Semiconductor – 64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO

1CY 7C40 9A
CY7C408A
CY7C409A
64 x 8 Cascadable FIFO
64 x 9 Cascadable FIFO
Features
• 64 x 8 and 64 x 9 first-in first-out (FIFO) buffer memory
• 35-MHz shift in and shift out rates
• Almost Full/Almost Empty and Half Full flags
• Dual-port RAM architecture
• Fast (50-ns) bubble-through
• Independent asynchronous inputs and outputs
• Output enable (CY7C408A)
• Expandable in word width and FIFO depth
• 5V ± 10% supply
• TTL complete
• Capable of withstanding greater than 2001V electro-
static discharge voltage
• 300-mil, 28-pin DIP
Functional Description
The CY7C408A and CY7C409A are 64-word deep by 8- or
9-bit wide first-in first-out (FIFO) buffer memories. In addition
to the industry-standard handshaking signals, almost full/al-
most empty (AFE) and half-full (HF) flags are provided.
AFE is HIGH when the FIFO is almost full or almost empty,
otherwise AFE is LOW. HF is HIGH when the FIFO is half full,
otherwise HF is LOW.
The CY7C408A has an output enable (OE) function.
The memory accepts 8- or 9-bit parallel words as its inputs (DI₀
– DI₈) under the control of the shift in (SI) input when the input
ready (IR) control signal is HIGH. The data is output, in the
same order as it was stored on the DO₀ – DO₈ output pins
under the control of the shift out (SO) input when the output
ready (OR) control signal is HIGH. If the FIFO is full (IR LOW),
pulses at the SI input are ignored; if the FIFO is empty (OR
LOW), pulses at the SO input are ignored.
The IR and OR signals are also used to connect the FIFOs in
parallel to make a wider word or in series to make a deeper
buffer, or both.
Parallel expansion for wider words is implemented by logically
ANDing the IR an OR outputs (respectively) of the individual
FIFOs together (Figure 5). The AND operation insures that all
of the FIFOs are either ready to accept more data (IR HIGH)
or ready to output data (OR HIGH) and thus compensate for
variations in propagation delay times between devices.
Serial expansion (cascading) for deeper buffer memories is
accomplished by connecting data outputs of the FIFO closet
to the data source (upstream device) to the data inputs of the
following (downstream) FIFO (Figure 4). In addition, to insure
proper operation, the SO signal of the upstream FIFO must be
connected to the OR output of the upstream FIFO. In this serial
expansion configuration, the IR and OR signals are used to
pass data through the FIFOs.
Reading and writing operations are completely asynchronous,
allowing the FIFO to be used as a buffer between two digital
machines of widely differing operating frequencies. The high
shift in and shift out rates of these FIFOs, and their throughput
rate due to the fast bubblethrough time, which is due to their
dual-port RAM architecture, make them ideal for high-speed
communications and controllers.
Logic Block Diagram
Pin Configurations
SI
IR
DI _.0
.
.
DI ₇
(7C409A)DI ₈
MR
HF
L
L
H
H
INPUT
CONTROL
LOGIC
WRITE POINTER
WRITE MULTIPLEXER
DATA IN
MEMORY
ARRAY
MASTER
RESET
READ MULTIPLEXER
READ POINTER
Flag Definitions
AFE
Words Stored
H
0-8
L
9 - 31
L
32 - 55
H
56 - 64
ALMOST FULL/
ALMOST EMPTY
HALF FULL
DATA OUT
OUTPUT
CONTROL
LOGIC
AFE
AFE
HF
IR
HF
SI
DO. ₀
.
.
DI 0
DI 1
GND
DO ₇
DI 2
DI 3
DO8 (7C409A)
DI ₄
DI ₅
OE (7C408A)
DI 6
DI 7
OR
(7C408A) NC
SO
(7C409A) DI8
C408A–1
1
28
2
27
3
26
4
25
5
24
6
23
7
7C408A
7C409A
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
MR
SO
OR
DO0
DO1
GND
DO2
DO3
DO4
DO5
DO6
DO7
OE (7C408A)
DO8 (7C409A)
C408A–3
DI 0
DI ₁
GND
DI ₂
DI 3
DI 4
DI ₅
4 3 2 1 28 27 26
5
25
6
24
7
8
7C408A
7C409A
23
22
9
21
10
20
11
19
12 13 14 15 1617 18
OR
DO ₀
DO 1
GND
DO 2
DO ₃
DO ₄
C408A–2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 1986 – Revised July 1994