CY7C375I Datasheet, PDF (1/17 Pages) Cypress Semiconductor – UltraLogic 128-Macrocell Flash CPLD

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CY7C375i
UltraLogic™ 128-Macrocell Flash CPLD
Features
• 128 macrocells in eight logic blocks
• 128 I/O pins
• Five dedicated inputs including 4 clock pins
• In-System Reprogrammable (ISR™) Flash technology
— JTAG Interface
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
— f_MAX = 125 MHz
— t_PD = 10 ns
— t_S = 5.5 ns
— t_CO = 6.5 ns
• Fully PCI compliant
• 3.3V or 5.0V I/O operation
• Available in 160-pin TQFP, CQFP, and PGA packages
Functional Description
The CY7C375i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
FLASH370i™ family of high-density, high-speed CPLDs. Like
all members of the FLASH370i family, the CY7C375i is
designed to bring the ease of use and high performance of the
22V10 to high-density PLDs.
Like all of the UltraLogic™ FLASH370i devices, the CY7C375i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins. The ISR interface is enabled
using the programming voltage pin (ISR_EN). Additionally,
because of the superior routability of the FLASH370i devices,
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
Logic Block Diagram
Clock
Inputs Inputs
1
INPUT
MACROCELL
4
4
INPUT/CLOCK
MACROCELLS
4
16 I/Os
I/O₀–I/O₁₅
LOGIC
LOGIC
BLOCK
36
36
BLOCK
A
16
PIM
16
H
16 I/Os
I/O₁₁₂–I/O₁₂₇
16 I/Os
I/O₁₆–I/O₃₁
LOGIC
BLOCK
36
B
16
LOGIC
36
BLOCK
G
16
16 I/Os
I/O₉₆–I/O₁₁₁
16 I/Os
I/O₃₂–I/O₄₇
LOGIC
BLOCK
36
C
16
LOGIC
36
BLOCK
F
16
16 I/Os
I/O₈₀–I/O₉₅
16 I/Os
I/O₄₈–I/O₆₃
LOGIC
BLOCK
36
D
16
64
LOGIC
36
BLOCK
E
16
64
16 I/Os
I/O₆₄–I/O₇₉
Selection Guide
7C375i–125 7C375i–100 7C375i–83
Maximum Propagation Delay^[1], t_PD
10
12
15
Minimum Set-Up, t_S
5.5
6
8
Maximum Clock to Output^[1], t_CO
6.5
7
8
Typical Supply Current, I_CC
125
125
125
Note:
1. The 3.3V I/O mode timing adder, t_3.3IO, must be added to this specification when V_CCIO = 3.3V
7C375iL–83
15
8
8
75
7C375i–66
20
10
10
125
7C375iL–66
20
10
10
75
Unit
ns
ns
ns
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03029 Rev. *A
Revised May 10, 2004