CY7C374I_04 Datasheet, PDF (1/15 Pages) Cypress Semiconductor – UltraLogic™ 128-Macrocell Flash CPLD

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CY7C374i
UltraLogic™ 128-Macrocell Flash CPLD
Features
Functional Description
• 128 macrocells in eight logic blocks
• 64 I/O pins
• Five dedicated inputs including four clock pins
• In-System Reprogrammable™ (ISR™) Flash technology
— JTAG interface
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
— f_MAX = 125 MHz
— t_PD = 10 ns
— t_S = 5.5 ns
— t_CO = 6.5 ns
• Fully PCI-compliant
• 3.3V or 5.0V I/O operation
• Available in 84-pin PLCC, 84-pin CLCC, and 100-pin
TQFP packages
• Pin-compatible with the CY7C373i
The CY7C374i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
FLASH370i™ family of high-density, high-speed CPLDs. Like
all members of the FLASH370i family, the CY7C374i is
designed to bring the ease of use as well as PCI Local Bus
Specification support and high performance of the 22V10 to
high-density CPLDs.
Like all of the UltraLogic™ FLASH370i devices, the CY7C374i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows, thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pin. The ISR interface is enabled
using the programming voltage pin (ISR_EN). Additionally,
because of the superior routability of the FLASH370i devices,
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
The 128 macrocells in the CY7C374i are divided between
eight logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
Logic Block Diagram
Clock
Inputs Inputs
1
INPUT
MACROCELL
4
4
INPUT/CLOCK
MACROCELLS
4
8 I/Os
I/O₀–I/O₇
LOGIC
LOGIC
BLOCK
36
36
BLOCK
A
16
PIM
16
H
8 I/Os
I/O₅₆–I/O₆₃
8 I/Os
I/O₈–I/O₁₅
LOGIC
BLOCK
36
B
16
LOGIC
36
BLOCK
G
16
8 I/Os
I/O₄₈–I/O₅₅
8 I/Os
I/O₁₆–I/O₂₃
LOGIC
BLOCK
36
C
16
LOGIC
36
BLOCK
F
16
8 I/Os
I/O₄₀–I/O₄₇
8 I/Os
I/O₂₄–I/O₃₁
LOGIC
BLOCK
36
D
16
32
LOGIC
36
BLOCK
E
16
32
8 I/Os
I/O₃₂–I/O₃₉
Selection Guide
7C374i–125 7C374i–100 7C374i–83 7C7374iL–83
Maximum Propagation Delay^[1], t_PD
10
12
15
15
Minimum Set-up, t_S
5.5
6
8
8
Maximum Clock to Output^[1], t_CO
6.5
7
8
8
Typical Supply Current, I_CC
125
125
125
75
Note:
1. The 3.3V I/O mode timing adder, t_3.3IO, must be added to this specification when V_CCIO = 3.3V.
7C374i–66
20
10
10
125
7C374iL–66
20
10
10
75
Unit
ns
ns
ns
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03031 Rev. *A
Revised April 19, 2004