CY7C374I Datasheet, PDF (1/13 Pages) Cypress Semiconductor – UltraLogic 128-Macrocell Flash CPLD

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CY7C374i
UltraLogic™ 128-Macrocell Flash CPLD
Features
• 128 macrocells in eight logic blocks
• 64 I/O pins
• 5 dedicated inputs including 4 clock pins
• In-System Reprogrammable (ISR™) Flash technology
— JTAG interface
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
— f_MAX = 125 MHz
— t_PD = 10 ns
— t_S = 5.5 ns
— t_CO = 6.5 ns
• Fully PCI compliant
• 3.3V or 5.0V I/O operation
• Available in 84-pin PLCC, 84-pin CLCC, and 100-pin
TQFP packages
• Pin compatible with the CY7C373i
Functional Description
The CY7C374i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
FLASH370i™ family of high-density, high-speed CPLDs. Like
all members of the FLASH370i family, the CY7C374i is de-
signed to bring the ease of use as well as PCI Local Bus Spec-
ification support and high performance of the 22V10 to
high-density CPLDs.
Like all of the UltraLogic™ FLASH370i devices, the CY7C374i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pin. The ISR interface is enabled
using the programming voltage pin (ISR_EN). Additionally, be-
cause of the superior routability of the FLASH370i devices, ISR
often allows users to change existing logic designs while si-
multaneously fixing pinout assignments.
The 128 macrocells in the CY7C374i are divided between
eight logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
Logic Block Diagram
CLOCK
INPUTS INPUTS
8 I/Os
I/O₀–I/O₇
1
INPUT
MACROCELL
4
LOGIC
BLOCK
36
A
16
PIM
4
INPUT/CLOCK
MACROCELLS
4
LOGIC
36
BLOCK
H
16
8 I/Os
I/O₈–I/O₁₅
LOGIC
BLOCK
36
B
16
LOGIC
36
BLOCK
G
16
8 I/Os
I/O₁₆–I/O₂₃
LOGIC
BLOCK
36
C
16
LOGIC
36
BLOCK
F
16
8 I/Os
I/O₂₄–I/O₃₁
LOGIC
BLOCK
36
D
16
32
LOGIC
36
BLOCK
E
16
32
Selection Guide
7C374i–125 7C374i–100
Maximum Propagation Delay^[1], t_PD (ns)
10
12
Minimum Set-Up, t_S (ns)
Maximum Clock to Output^[1], t_CO (ns)
5.5
6
6.5
7
Typical Supply Current, I_CC (mA)
125
125
Note:
1. The 3.3V I/O mode timing adder, t_3.3IO, must be added to this specification when VCCIO = 3.3V.
7C374i–83
15
8
8
125
8 I/Os
I/O₅₆–I/O₆₃
8 I/Os
I/O₄₈–I/O₅₅
8 I/Os
I/O₄₀–I/O₄₇
8 I/Os
I/O₃₂–I/O₃₉
7C374i-1
7C374i–66
20
10
10
125
7C374iL–66
20
10
10
75
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 1995 – Revised December 19, 1997