CY7C371I Datasheet, PDF (1/12 Pages) Cypress Semiconductor – UltraLogic 32-Macrocell Flash CPLD

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CY7C371i
UltraLogic™ 32-Macrocell Flash CPLD
Features
• 32 macrocells in two logic blocks
• 32 I/O pins
• Five dedicated inputs including two clock pins
• In-System Reprogrammable (ISR™) Flash technology
— JTAG interface
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
— f_MAX = 143 MHz
— t_PD= 8.5 n3s
— t_S = 5 ns
— t_CO = 6 ns
• Fully PCI-compliant
• 3.3V or 5.0V I/O operation
• Available in 44-pin PLCC, and TQFP packages
• Pin-compatible with the CY7C372i
Functional Description
The CY7C371i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
FLASH370i™ family of high-density, high-speed CPLDs. Like
all members of the FLASH370i family, the CY7C371i is
designed to bring the ease of use and high performance of the
22V10, as well as PCI Local Bus Specification support, to
high-density CPLDs.
Like all of the UltraLogic™ FLASH370i devices, the CY7C371i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows, thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins. The ISR interface is enabled
using the programming voltage pin (ISR_EN). Additionally,
because of the superior routability of the FLASH370i devices,
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
The 32 macrocells in the CY7C371i are divided between two
logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
The logic blocks in the FLASH370i architecture are connected
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the inter-
connect.
Like all members of the FLASH370i family, the CY7C371i is rich
in I/O resources. Each macrocell in the device features an
associated I/O pin, resulting in 32 I/O pins on the CY7C371i.
In addition, there are three dedicated inputs and two
input/clock pins.
Logic Block Diagram
Clock
Inputs Inputs
16 I/Os
I/O₀–I/O₁₅
3
INPUT
MACROCELLS
2
LOGIC
BLOCK
36
PIM
A
16
2
INPUT/CLOCK
MACROCELLS
2
LOGIC
36
BLOCK
B
16
16 I/Os
I/O₁₆–I/O₃₁
16
16
Selection Guide
7C371i-143 7C371i-110 7C371i-83 7C371iL-83 7C371i-66 7C371iL-66
Maximum Propagation Delay^[1], t_PD
8.5
10
12
12
15
15
Minimum Set-up, t_S
Maximum Clock to Output^[1], t_CO
5
6
8
6
6.5
8
8
10
10
8
10
10
Typical Supply Current, I_CC Comm./Ind.
75
75
75
45
75
45
Note:
1. The 3.3V I/O mode timing adder, t_3.3IO, must be added to this specification when V_CCIO = 3.3V.
Unit
ns
ns
ns
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03032 Rev. *A
Revised April 19, 2004