CY7C371 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – UltraLogic 32-Macrocell Flash CPLD

7c371: Tuesday, May 26, 1992
Revision: August 9, 1995
CY7C371
t UltraLogic 32ĆMacrocell Flash CPLD
Features
D 32 macrocells in two logic blocks
D 32 I/O pins
D 6 dedicated inputs including 2 clock
pins
D No hidden delays
D High speed
Ċ f_MAX = 143 MHz
Ċ t_PD= 8.5 ns
Ċ t_S = 5 ns
Ċ t_CO = 6 ns
D Electrically alterable FLASH
technology
D Available in 44Ćpin PLCC, CLCC, and
TQFP packages
D Pin compatible with the CY7C372
Functional Description
The CY7C371 is a Flash erasable Complex
Programmable Logic Device (CPLD) and
is part of the FLASH370 family of highĆdenĆ
sity, highĆspeed CPLDs. Like all members
of the FLASH370 family, the CY7C371 is
designed to bring the ease of use and high
performance of the 22V10 to highĆdensity
CPLDs.
The 32 macrocells in the CY7C371 are diĆ
vided between two logic blocks. Each logic
block includes 16 macrocells, a 72 x 86
product term array, and an intelligent
product term allocator.
The logic blocks in the FLASH370 architecĆ
ture are connected with an extremely fast
and predictable routing resourceĊthe
Programmable Interconnect Matrix
(PIM). The PIM brings flexibility, routĆ
ability, speed, and a uniform delay to the
interconnect.
Like all members of the FLASH370 family,
the CY7C371 is rich in I/O resources.
Each macrocell in the device features an
associated I/O pin, resulting in 32 I/O pins
on the CY7C371. In addition, there are
four dedicated inputs and two input/clock
pins.
Finally, the CY7C371 features a very simĆ
ple timing model. Unlike other highĆdenĆ
sity CPLD architectures, there are no hidĆ
den speed delays such as fanout effects, inĆ
terconnect delays, or expander delays. ReĆ
gardless of the number of resources used
or the type of application, the timing paĆ
rameters on the CY7C371 remain the
same.
Logic Block Diagram
INPUTS
4
INPUT
MACROCELLS
CLOCK
INPUTS
2
INPUT/CLOCK
MACROCELLS
16 I/Os
I/O₀-I/O₁₅
2
LOGIC
BLOCK
A
16
PIM
36
16
2
36
16
LOGIC
BLOCK
B
16
7c371Ć1
16 I/Os
I/O₁₆-I/O₃₁
Selection Guide
7C371-143
Maximum Propagation Delay, t_PD (ns)
Minimum SetĆUp, t_S (ns)
Maximum Clock to Output, t_CO (ns)
Maximum Supply
Current, I_CC (mA)
Commercial
Military/Ind.
Shaded area contains preliminary information.
8.5
5
6
220
7C371-110
10
6
6.5
175
7C371-83
12
10
10
175
220
7C371L-83
12
10
10
90
110
7C371-66
15
12
12
175
220
7C371L-66
15
12
12
90
110
Cypress Semiconductor Corporation
D
3901 North First Street
1
D D D San Jose
CA 95134
408-943-2600
December 1993 - Revised August 1995