CY7C346B-35NC Datasheet, PDF (1/6 Pages) Cypress Semiconductor – Multiple Array Matrix High-Density EPLDs

E PL D
CY7C340 EPLD Family
Multiple Array Matrix High-Density EPLDs
Features
• Erasable, user-configurable CMOS EPLDs capable of
implementing high-density custom logic functions
• 0.8-micron double-metal CMOS EPROM technology
(CY7C34X)
• Advanced 0.65-micron CMOS technology to increase
performance (CY7C34XB)
• Multiple Array MatriX architecture optimized for speed,
density, and straightforward design implementation
— Programmable Interconnect Array (PIA) simplifies
routing
— Flexible macrocells increase utilization
— Programmable clock control
— Expander product terms implement complex logic
functions
General Description
The Cypress Multiple Array Matrix (MAX®) family of EPLDs
provides a user-configurable, high-density solution to gener-
al-purpose logic integration requirements. With the combina-
tion of innovative architecture and state-of-the-art process, the
MAX EPLDs offer LSI density without sacrificing speed.
The MAX architecture makes it ideal for replacing large
amounts of TTL SSI and MSI logic. For example, a 74161
counter utilizes only 3% of the 128 macrocells available in the
CY7C342B. Similarly, a 74151 8-to-1 multiplexer consumes
less than 1% of the over 1,000 product terms in the
Max Family Members
CY7C342B. This allows the designer to replace 50 or more
TTL packages with just one MAX EPLD. The family comes in
a range of densities, shown below. By standardizing on a few
MAX building blocks, the designer can replace hundreds of
different 7400 series part numbers currently used in most dig-
ital systems.
The family is based on an architecture of flexible macrocells
grouped together into Logic Array Blocks (LABs). Within the
LAB is a group of additional product terms called expander
product terms. These expanders are used and shared by the
macrocells, allowing complex functions of up to 35 product
terms to be easily implemented in a single macrocell. A Pro-
grammable Interconnect Array (PIA) globally routes all signals
within devices containing more than one LAB. This architec-
ture is fabricated on the Cypress 0.8-micron, double-lay-
er-metal CMOS EPROM process, yielding devices with signif-
icantly higher integration, density and system clock speed than
the largest of previous generation EPLDs. The CY7C34XB de-
vices are 0.65-micron shrinks of the original 0.8-micron family.
The CY7C34XBs offer faster speed bins for each device in the
Cypress MAX family.
The density and performance of the CY7C340 family is ac-
cessed using Cypress’s Warp™, Warp Professional™, or
Warp Enterprise™ design software. Warp provides
state-of-the-art synthesis, fitting, simulation and other devel-
opment tools at a very low cost. Warp Professional or Warp
Enterprise are sophisticated CAE tool that include behavior-
al simulation, graphical waveform editing and more. Consult
the datasheets for Warp, Warp Professional and Warp Enter-
prise™ for more information about these development tools.
Feature
CY7C344(B)
CY7C343(B)
CY7C342B
CY7C346(B)
CY7C341B
Macrocells
32
64
128
128
192
MAX Flip-Flops
32
MAX Latches^[1]
64
MAX Inputs^[2]
23
64
128
128
192
128
256
256
384
35
59
84
71
MAX Outputs
16
28
52
64
64
Packages
28H,J,W,P
44H,J
68H,J,R
84H,J 100R,N
84H,J,R
Key: P—Plastic DIP; H—Windowed Ceramic Leaded Chip Carrier; J—Plastic J-Lead Chip Carrier; R—Windowed Pin Grid Array;
W—Windowed Ceramic DIP; N—Plastic Quad Flat Pack
Notes:
1. When all expander product terms are used to implement latches.
2. With one output.
PAL is a registered trademark of Advanced Micro Devices.
MAX is a registered trademark of Altera Corporation.
FLASH370, Warp, Warp Professional, and Warp Enterprise are trademarks of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 19, 2000