CY7C344B_05 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 32-Macrocell MAX® EPLD

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CY7C344B
32-Macrocell MAX^® EPLD
Features
• High-performance, high-density replacement for TTL,
74HC, and custom logic
• 32 macrocells, 64 expander product terms in one LAB
• 8 dedicated inputs, 16 I/O pins
• Advanced 0.65-micron CMOS EPROM technology to
increase performance
• 28-pin, 300-mil DIP, cerDIP or 28-pin HLCC, PLCC
package
Functional Description
Available in a 28-pin, 300-mil DIP or windowed J-leaded
ceramic chip carrier (HLCC), the CY7C344B represents the
Logic Block Diagram^[1]
densest EPLD of this size. Eight dedicated inputs and 16
bidirectional I/O pins communicate to one logic array block. In
the CY7C344B LAB there are 32 macrocells and 64 expander
product terms. When an I/O macrocell is used as an input, two
expanders are used to create an input path. Even if all of the
I/O pins are driven by macrocell registers, there are still 16
“buried” registers available. All inputs, macrocells, and I/O pins
are interconnected within the LAB.
The speed and density of the CY7C344B makes it a natural
for all types of applications. With just this one device, the
designer can implement complex state machines, registered
logic, and combinatorial “glue” logic, without using multiple
chips. This architectural flexibility allows the CY7C344B to
replace multichip TTL solutions, whether they are
synchronous, asynchronous, combinatorial, or all three.
Pin Configurations
15(22)
15(23)
27(6)
28(7)
INPUT
INPUT
INPUT
INPUT
INPUT
1(8)
INPUT/CLK 2(9)
INPUT
13(20)
INPUT
14(21)
MACROCELL 2
MACROCELL 1
MACROCELL 4
MACROCELL 3
MACROCELL 6
G
MACROCELL 5
I
MACROCELL 8
L
MACROCELL 7
O
O
MACROCELL 10
MACROCELL 9
MACROCELL 12
B
MACROCELL 11
C
MACROCELL 14
MACROCELL 16
A
L
MACROCELL 13
O
MACROCELL 15
N
MACROCELL 18
B
MACROCELL 20
U
MACROCELL 22
S
MACROCELL 24
MACROCELL 17
T
MACROCELL 19
R
MACROCELL 21
O
L
MACROCELL 23
MACROCELL 26
MACROCELL 25
MACROCELL 28
MACROCELL 27
MACROCELL 30
MACROCELL 29
MACROCELL 32
MACROCELL 31
64 EXPANDER PRODUCT TERM ARRAY
32
HLCC
Top View
I/O 3(10)
I/O 4(11)
I/O 5(12)
I/O 6(13)
I/O 9(16)
I/O 10(17)
I/O 11(18)
I/O 12(19)
I/O 17(24)
I/O 18(25)
I/O 19(26)
I/O 20(27)
I/O 23(2)
I/O 24(3)
I/O 25(4)
I/O 26(5)
I/O
INPUT
INPUT
INPUT
INPUT/CLK
I/O
I/O
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
12
13
14 1516
1718 ¹⁹
I/O
I/O
INPUT
INPUT
INPUT
INPUT
I/O
CerDIP
Top View
INPUT 1
INPUT/CLK 2
I/O ₃
I/O 4
I/O ₅
I/O 6
V_{CC 7}
GND ₈
I/O ₉
I/O 10
I/O 11
I/O 12
INPUT ₁₃
INPUT 14
28 INPUT
27 INPUT
26 ^I/O
25 I/O
24 ^I/O
23 I/O
22 ^VCC
21 ^GND
20 ^I/O
19 I/O
18 I/O
17 I/O
16 ^INPUT
15 INPUT
Selection Guide
Maximum Access Time
Note:
1. Number in () refers to J-leaded packages.
7C344B-15
15
7C344B-20
20
7C344B-25
Unit
25
ns
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03036 Rev. *D
Revised June 6, 2005