CY7C291A_06 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 2K x 8 Reprogrammable PROM

CY7C291A
2K x 8 Reprogrammable PROM
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
— 20 ns (Commercial)
— 35 ns (Military)
• Low power
— 660 mW (Commercial and Military)
• Low standby power
— 220 mW (Commercial and Military)
• EPROM technology 100% programmable
• Slim 300-mil or standard 600-mil packaging available
• 5V ±10% V_CC, commercial and military
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
• Capable of withstanding >2001V static discharge
Logic Block Diagram
A₀
A₁
A₂
ROW
A₃
ADDRESS
A₄
A₅
A₆
ADDRESS
DECODER
A₇
A₈
A₉
COLUMN
ADDRESS
A₁₀
PROGRAM-
MABLE
ARRAY
MULTI-
PLEXER
POWER
DOWN
7C293A
CS₁
CS₂
CS₃
Functional Description
The CY7C291A is a high-performance 2K-word by 8-bit
CMOS PROM. It is packaged in a 300-mil ceramic package
which may be equipped with an erasure window; when
exposed to UV light the PROM is erased and can then be
reprogrammed. The memory cells utilize proven EPROM
floating-gate technology and byte-wide intelligent
programming algorithms.
The CY7C291A is a plug-in replacement for bipolar devices
and offers the advantage of lower power, reprogrammability,
superior performance and programming yield. The EPROM
cell requires only 12.5V for the supervoltage and low current
requirements allow for gang programming. The EPROM cells
allow for each memory location to be tested 100%, as each
location is written into, erased, and repeatedly exercised prior
to encapsulation. Each PROM is also tested for AC perfor-
mance to guarantee that after customer programming the
product will meet DC and AC specification limits.
A read is accomplished by placing an active LOW signal on
CS₁, and active HIGH signals on CS₂ and CS₃. The contents
of the memory location addressed by the address line
(A₀−A₁₀) will become available on the output lines (O₀−O₇).
Pin Configurations
O₇
DIP
Top View
LCC/PLCC (Opaque Only)
Top View
O₆
A₇ 1
24 ^VCC
A₆ 2
23 ^A8
O₅
O₄
O₃
A₅ 3 _7C291A 22 ^A9
A₄ 4
21 ^A10
A₃ 5
20 ^CS1
4 3 2 1 28 27 26
A₄ 5
25 ^A10
A₃ 6 _7C291A
24 CS1
A₂ 6
A₁ 7
A₀ 8
19 ^CS2
18 ^CS3
17 O7
A_{2 7}
A_{1 8}
A_{0 9}
NC ₁₀
23 CS2
22 ^CS3
21 NC
20 O7
O₀ 9
O₁ 10
16 ^O6
15 ^O5
O_{0 11}
19 O₆
12 1314151617 18
O₂
O₂ 11
14 O₄
GND 12
13 O₃
O₁
O₀
Window available
Cypress Semiconductor Corporation
Document #: 38-04011 Rev. *B
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised August 17, 2006
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