CY7C291A-293A Datasheet, PDF (1/15 Pages) Cypress Semiconductor – 2K x 8 Reprogrammable PROM

1CY 7C29 2A
CY7C291A
CY7C292A/CY7C293A
2K x 8 Reprogrammable PROM
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
— 20 ns (commercial)
— 25 ns (military)
• Low power
— 660 mW (commercial and military)
• Low standby power
— 220 mW (commercial and military)
• EPROM technology 100% programmable
• Slim 300-mil or standard 600-mil packaging available
• 5V ±10% V_CC, commercial and military
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
• Capable of withstanding >2001V static discharge
Functional Description
The CY7C291A, CY7C292A, and CY7C293A are high-perfor-
mance 2K-word by 8-bit CMOS PROMs. They are functionally
identical, but are packaged in 300-mil (7C291A, 7C293A) and
600-mil wide plastic and hermetic DIP packages (7C292A).
The CY7C293A has an automatic power down feature which
reduces the power consumption by over 70% when deselect-
ed. The 300-mil ceramic package may be equipped with an
erasure window; when exposed to UV light the PROM is
erased and can then be reprogrammed. The memory cells uti-
lize proven EPROM floating-gate technology and byte-wide in-
telligent programming algorithms.
The CY7C291A, CY7C292A, and CY7C293A are plug-in re-
placements for bipolar devices and offer the advantages of
lower power, reprogrammability, superior performance and
programming yield. The EPROM cell requires only 12.5V for
the supervoltage and low current requirements allow for gang
programming. The EPROM cells allow for each memory loca-
tion to be tested 100%, as each location is written into, erased,
and repeatedly exercised prior to encapsulation. Each PROM
is also tested for AC performance to guarantee that after cus-
tomer programming the product will meet DC and AC specifi-
cation limits.
A read is accomplished by placing an active LOW signal on
CS₁, and active HIGH signals on CS₂ and CS₃. The contents
of the memory location addressed by the address line (A₀ −
A₁₀) will become available on the output lines (O₀ − O₇).
Logic Block Diagram
A₀
A₁
A₂
ROW
A3
ADDRESS
A₄
A₅
A₆
ADDRESS
DECODER
A₇
A₈
A₉
COLUMN
ADDRESS
A₁₀
PROGRAM-
MABLE
ARRAY
MULTI-
PLEXER
POWER
DOWN
7C293A
CS₁
CS₂
CS₃
Pin Configurations
O₇
DIP
Top View
O₆
A₇ 1
24 ^VCC
A₆ 2
23 ^A8
O₅
A₅ 3 _7C291A 22 ^A9
A4 4 ^7C292A 21 ^A10
A₃ 5 ^7C293A 20 ^CS1
O₄
A₂ 6
19 ^CS2
A1 7
18 ^CS3
O₃
A₀ 8
17 O7
O₀ 9
16 ^O6
O₁ 10
15 ^O5
O₂
O₂ 11
14 O₄
GND 12
13 O₃
O₁
C291A-2
O₀
C291A-1
LCC/PLCC (Opaque Only)
Top View
4 3 2 1 28 27 26
A₄ 5
25 ^A10
A₃ 6
A_{2 7}
A_{1 8}
7C291A
24 CS1
23 CS2
22 ^CS3
A_{0 9}
NC ₁₀ ^7C293A
21 NC
20 O7
O_{0 11}
19 O₆
12 1314151617 18
C291A-3
Window available on
7C291A and 7C293A
only.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 1986 – Revised May 1993