CY7C287 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – 64K x 8 Reprogrammable Registered PROM

1CY 7C28 7
CY7C287
64K x 8 Reprogrammable Registered PROM
Features
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
— t_SA = 45 ns
— t_CO = 15 ns
• Low power
— 120 mA
• On-chip, edge-triggered output registers
• Programmable synchronous or asynchronous output
enable
• EPROM technology, 100% programmable
• 5V ±10% V_CC, commercial and military
• TTL-compatible I/O
• Slim 300-mil package
• Capable of withstanding >2001V static discharge
Functional Description
The CY7C287 is a high-performance 64K x 8 CMOS PROM.
The CY7C287 is equipped with an output register and an out-
put enable that can be programmed to be synchronous (E_S) or
asynchronous (E). It is available in a 28-pin, 300-mil package.
The address set-up time is 45 ns and the time from clock HIGH
to output valid is 15 ns.
The CY7C287 is available in a cerDIP package equipped with
an erasure window to provide reprogrammability. When ex-
posed to UV light, the PROM is erased and can be repro-
grammed. The memory cells utilize proven EPROM float-
ing-gate technology and byte-wide intelligent programming
algorithms.
The CY7C287 offers the advantage of low power, superior per-
formance, and programming yield. The EPROM cell requires
only 12.5V for the supervoltage and low current requirements
allow for gang programming. The EPROM cells allow for each
memory location to be 100% tested with each cell being pro-
grammed, erased, and repeatedly exercised prior to encapsu-
lation. Each PROM is also tested for AC performance to guar-
antee that the product will meet DC and AC specification
limits after customer programming.
Reading the CY7C287 is accomplished by placing an active
LOW signal on E/E_S. The contents of the memory location
addressed by the address lines (A₀ − A₁₅) will become
available on the output lines (O₀ − O₇) on the next rising of
CP.
Logic Block Diagram
A₁₅
A14
A₁₃
A12
A11
X
ROW
ADDRESS
512x 1024
PROGRAM-
MABLE
ARRAY
8 x 1 of 128
MULTI-
PLEXER
8
SENSE
AMPS
8-BIT
EDGE-
TRIGGERED
REGISTER
A10
A9
A8
ADDRESS
DECODER
A7
A6
A₅
A4
Y
COLUMN
A3
ADDRESS
A₂
A1
A0
E/ES
CP
OE
REGISTER
PROGRAMMABLE
MULTIPLEXER
C287-1
Pin Configurations
CerDIP
Top View
O₇
A9 1
28 V_CC
A₈ 2
27 A₁₀
O₆
A7 3
26 A₁₁
A₆ 4
25 A₁₂
O5
A5 5
24 A₁₃
A₄ 6 7C28723 _A14
O4
A3 7
A₂ 8
22 A₁₅
21 CP
O3
A1 9
A₀ 10
20 E/E_S
19 O₇
O0 11
18 O6
O2
O₁ 12
17 O5
O2 13
16 O4
O1
GND 14
15 O3
O0
C287-3
LCC/PLCC
Top View
A₅
A₄
A3
NC
A₂
A₁
A0
GND
O0
4 3 2 1 323130
5
29
6
7
7C287
28
27
8
26
9
25
10
24
11
23
12
22
13
21
14151617 181920
A₁₂
A₁₃
A₁₄
A₁₅
NC
CP
E/E_S
O7
GND
C287-2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
September 1994 – Revised December 1994