CY7C276 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 16K x 16 Reprogrammable PROM

1CY 7C27 6
CY7C276
16K x 16 Reprogrammable PROM
Features
• 0.8-micron CMOS for optimum speed/power
• High speed (for commercial and military)
— 25-ns access time
• 16-bit-wide words
• Three programmable chip selects
• Programmable output enable
• 44-pin PLCC and 44-pin LCC packages
• 100% reprogrammable in windowed packages
• TTL-compatible I/O
• Capable of withstanding greater than 2001V static dis-
charge
Functional Description
The CY7C276 is a high-performance 16K-word by 16-bit
CMOS PROM. It is available in a 44-pin PLCC/CLCC and a
44-pin LCC packages, and is 100% reprogrammable in win-
dowed packages. The memory cells utilize proven EPROM
floating gate technology and word-wide programming algo-
rithms.
The CY7C276 allows the user to independently program the
polarity of each chip select (CS₂−CS₀). This provides on-chip
decoding of up to eight banks of PROM. The polarity of the
asynchronous output enable pin (OE) is also programmable.
In order to read the CY7C276, all three chip selects must be
active and OE must be asserted. The contents of the memory
location addressed by the address lines (A₁₃−A₀) will become
available on the output lines (D₁₅−D₀). The data will remain on
the outputs until the address changes or the outputs are dis-
abled.
Logic Block Diagram
A₁₃
A₁₂
A₁₁
A₁₀
16K x 16
PROGRAMMABLE
ARRAY
A₉
A₈
A₇
A₆
A₅
A₄
A₃
A₂
A₁
A₀
CS₀
CS₁
CS
DECODE
CS₂
OE
D₁₅
D₁₄
D₁₃
D₁₂
D₁₁
D₁₀
D₉
D₈
D₇
D₆
D₅
D₄
D₃
D₂
D₁
D₀
C276–1
Pin Configuration
LCC/PLCC/CLCC
Top View
6 5 4 3 2 1 44 43 42 41 40
D_{12 7}
39 A13
D_{11 8}
38 A12
D_{10 9}
37 A11
D_{9 10}
36 A10
D_{8 11}
35 A9
V_{SS 12}
34 VSS
V_{CC 13}
33 VSS
D_{7 14}
32 A8
D_{6 15}
31 A7
D_{5 16}
30 A6
D_{4 17}
29 A5
18 19 20 21 22 23 24 25 26 27 28
C276–2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 1991 – Revised December 1993