CY7C271A Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 32K x 8 Power Switched and Reprogrammable PROM

1CY7C271A
CY7C271A
Features
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
— 25 ns (Commercial)
• Low power
— 275 mW (Commercial)
• Super low standby power
— Less than 85 mW when deselected
• EPROM technology 100%programmable
• Slim 300-mil package
• Direct replacement for bipolar PROMs
• Capable of withstanding >4001V static discharge
Functional Description
The CY7C271A is a high-performance 32,768-word by 8-bit
CMOS PROM. When disabled (CE HIGH), the 7C271A
Logic Block Diagram
A₁₄
A₁₃
A₁₂
A₁₁
A₁₀
X
ADDRESS
256 x 1024
PROGRAMABLE
ARRAY
8 x 1 OF 128
MULTIPLEXER
A₉
A₈
A₇
A₆
A₅
A₄
A₃
Y
A₂
ADDRESS
A₁
A₀
POWER-DOWN
CE
CS₁
CS₂
32K x 8 Power Switched and
Reprogrammable PROM
automatically powers down into a low-power stand-by mode.
The CY7C271A is packaged in the 300-mil slim package and
is available in a cerDIP package equipped with an erasure
window to provide for reprogrammability. When exposed to UV
light, the PROM is erased and can be reprogrammed. The
memory cells utilize proven EPROM floating gate technology
and byte-wide intelligent programming algorithms.
The CY7C271A offers the advantages of lower power,
superior performance, and programming yield. The EPROM
cell requires only 12.5V for the super voltage, and low current
requirements allow for gang programming. The EPROM cells
allow each memory location to be tested 100% because each
location is written into, erased, and repeatedly exercised prior
to encapsulation. Each PROM is also tested for AC perfor-
mance to guarantee that after customer programming, the
product will meet DC and AC specification limits.
Reading the 7C271A is accomplished by placing active LOW
signals on CS₁ and CE, and an active HIGH on CS₂. The
contents of the memory location addressed by the address
lines (A₀–A₁₄) will become available on the output lines
(O₀–O₇).
Pin Configurations
DIP/Flatpack
A₉ 1
28 VCC
O₇
A₈ 2
27 A10
A₇ 3
26 A11
A₆ 4
25 A12
O₆
A₅ 5
24 A13
A₄ 6
23 A14
A₃ 7
22 CS₁
O₅
A₂ 8
21 CS₂
A₁ 9
20 CE
A₀ 10
19 O₇
O₄
O₀ 11
18 O6
O₁ 12
17 O5
O₂ 13
16 O₄
O₃
GND 14
15 O3
O₂
PLCC
Top View
O₁
4 3 2 1 2827 26
A₄ 5
A_{3 6}
25 ^E
24 CLR
O₀
A_{2 7}
A_{1 8}
23 ES
22 ^CP
A_{0 9}
21 NC
NC ₁₀
20 O7
O₀
11
19
12 13141516 1718
O₆
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-04013 Rev. *B
Revised December 28, 2002