CY7C271 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 32K x 8 Power Switched and Reprogrammable PROM

1CY7C274
CY7C271
CY7C274
32K x 8 Power Switched and
Reprogrammable PROM
Features
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
— 30 ns (Commercial)
— 35 ns (Military)
• Low power
— 660 mW (commercial)
— 715 mW (military)
• Super low standby power
— Less than 165 mW when deselected
• EPROM technology 100% programmable
• Slim 300-mil package (7C271)
• Direct replacement for bipolar PROMs
• Capable of withstanding >2001V static discharge
Functional Description
The CY7C271 and CY7C274 are high-performance
32,768-word by 8-bit CMOS PROMs. When disabled (CE
HIGH), the 7C271/7C274 automatically powers down into a
low-power stand-by mode. The CY7C271 is packaged in the
300-mil slim package. The CY7C274 is packaged in the
industry standard 600-mil package. Both the CY7C271 and
CY7C274 are available in a cerDIP package equipped with an
erasure window to provide for reprogrammability. When
exposed to UV light, the PROM is erased and can be repro-
grammed. The memory cells utilize proven EPROM floating
gate technology and byte-wide intelligent programming
algorithms.
The CY7C271 and CY7C274 offer the advantage of lower
power, superior performance, and programming yield. The
EPROM cell requires only 12.5V for the super voltage, and low
current requirements allow for gang programming. The
EPROM cells allow each memory location to be tested 100%
because each location is written into, erased, and repeatedly
exercised prior to encapsulation. Each PROM is also tested
for AC performance to guarantee that after customer
programming, the product will meet DC and AC specification
limits.
Reading the 7C271 is accomplished by placing active LOW
signals on CS₁ and CE, and an active HIGH on CS₂. Reading the
7C274 is accomplished by placing active LOW signals on OE and
CE. The contents of the memory location addressed by the address
lines (A₀−A₁₄) will become available on the output lines (O₀−O₇).
Logic Block Diagram
A₁₄
A₁₃
A₁₂
X ADDRESS
A₁₁
A₁₀
256 x 1024
PROGRAMABLE
ARRAY
8 x 1 OF 128
MULTIPLEXER
A₉
A₈
A₇
A₆
A₅
A₄
A₃
Y ADDRESS
A₂
A₁
A₀
POWER-DOWN
CE
(7C271) CS₁
(7C271) CS₂
(7C274) OE
Pin Configurations
DIP/Flatpack
O₇
A₉ 1
28 VCC
A₈ 2
27 A10
A₇ 3
26 A11
O₆
A₆ 4
25 A12
A₅ 5
24 A13
A₄ 6 ^7C271 23 A₁₄
O₅
A₃ 7
22 CS₁
A₂ 8
21 CS₂
A₁ 9
20 CE
O₄
A₀ 10
O₀ 11
19 O₇
18 O6
O₁ 12
17 O5
O₂ 13
16 O₄
O₃
GND 14
15 O3
DIP/Flatpack
V_PP 1
A₁₂ 2
A₇ 3
28 VCC
27 A14
26 A13
A₆ 4
25 A8
A₅ 5
24 A9
A₄ 6 ^7C274 23 A₁₁
A₃ 7
22 OE
A₂ 8
21 A10
A₁ 9
20 CE
A₀ 10
O₀ 11
19 O₇
18 O6
O₁ 12
17 O5
O₂ 13
16 O₄
GND 14
15 O3
LCC/PLCC (Opaque Only) LCC/PLCC (Opaque Only)
O₂
4 3 2 1 32 31 30
4 3 2 1 32 31 30
O₁
A_{6 5}
A_{5 6}
A₄ 7
7C271
29 ^A12
28 ^A13
27 ^A14
A_{6 5}
A_{5 6}
A₄ 7
7C274
29 ^A8
28 ^A9
27 ^A11
A_{3 8}
26 NC
A_{3 8}
26 NC
O₀
A_{2 9}
A_{1 10}
25 CS1
24 ^CS2
A_{2 9}
A_{1 10}
25 OE
24 ^A10
A_{0 11}
23 CE
A_{0 11}
23 CE
NC 12
22 O7
NC 12
22 O7
O₀ 13
21 O₆
O₀ 13
21 O₆
14151617 181920
14151617 181920
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-04008 Rev. *B
Revised December 27, 2002