CY7C2670KV18 Datasheet, PDF (1/30 Pages) Cypress Semiconductor – 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

CY7C2670KV18
144-Mbit DDR II+ SRAM Two-Word Burst
Architecture (2.5 Cycle Read Latency) with ODT
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Features
■ 144-Mbit density (14 M × 36)
■ 550-MHz clock for high bandwidth
■ Two-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces (data transferred at
1100 MHz) at 550 MHz
■ Available in 2.5 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ On-die termination (ODT) feature
❐ Supported for D_[x:0], BWS_[x:0], and K/K inputs
■ Synchronous internally self-timed writes
■ DDR II+ operates with 2.5-cycle read latency when DOFF is
asserted high
■ Operates similar to DDR I device with 1 cycle read latency when
DOFF is asserted low
■ Core V_DD = 1.8 V ± 0.1 V; I/O V_DDQ = 1.4 V to V_DD[1]
❐ Supports both 1.5 V and 1.8 V I/O supply
■ High-speed transceiver logic (HSTL) inputs and variable drive
HSTL output buffers
■ Available in 165-ball fine-pitch ball grid array (FBGA) package
(15 × 17 × 1.4 mm)
■ Offered in non Pb-free package.
■ JTAG 1149.1 compatible test access port
■ Phase locked loop (PLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C2670KV18 – 4 M × 36
Functional Description
The CY7C2670KV18 is 1.8-V synchronous pipelined SRAM
equipped with DDR II+ architecture. The DDR II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of K and K. Each address location is associated with two 36-bit
words (CY7C2670KV18) that burst sequentially into or out of the
device.
These devices have an ODT feature supported for D_[x:0],
BWS_[x:0], and K/K inputs, which helps eliminate external
termination resistors, reduce cost, reduce board area, and
simplify board routing.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
Maximum operating frequency
Maximum operating current
Description
× 36
550 MHz
550
1140
450 MHz
450
980
Unit
MHz
mA
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V_DDQ = 1.4 V to V_DD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-44143 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 1, 2012