CY7C263-45DMB Datasheet, PDF (1/16 Pages) Cypress Semiconductor – 8K x 8 Power-Switched and Reprogrammable PROM

CY7C261
CY7C263/CY7C264
8K x 8 Power-Switched and Reprogrammable PROM
Features
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
— 20 ns (commercial)
— 25 ns (military)
• Low power
— 660 mW (commercial)
— 770 mW (military)
• Super low standby power (7C261)
— Less than 220 mW when deselected
— Fast access: 20 ns
• EPROM technology 100% programmable
• Slim 300-mil or standard 600-mil packaging available
• 5V ± 10% V_CC, commercial and military
• Capable of withstanding greater than 2001V static dis-
charge
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
Functional Description
The CY7C261, CY7C263, and CY7C264 are high-perfor-
mance 8192-word by 8-bit CMOS PROMs. When deselected,
the 7C261 automatically powers down into a low-power stand-
by mode. It is packaged in a 300-mil-wide package. The 7C263
and 7C264 are packaged in 300-mil-wide and 600-mil-wide
packages respectively, and do not power down when deselect-
ed. The reprogrammable packages are equipped with an era-
sure window; when exposed to UV light, these PROMs are
erased and can then be reprogrammed. The memory cells uti-
lize proven EPROM floating-gate technology and byte-wide in-
telligent programming algorithms.
The CY7C261, CY7C263, and CY7C264 are plug-in replace-
ments for bipolar devices and offer the advantages of lower
power, superior performance and programming yield. The
EPROM cell requires only 12.5V for the supervoltage and low
current requirements allow for gang programming. The
EPROM cells allow for each memory location to be tested
100%, as each location is written into, erased, and repeatedly
exercised prior to encapsulation. Each PROM is also tested for
AC performance to guarantee that after customer program-
ming the product will meet DC and AC specification limits.
Read is accomplished by placing an active LOW signal on CS.
The contents of the memory location addressed by the ad-
dress line (A₀−A₁₂) will become available on the output lines
(O₀−O₇).
Logic Block Diagram
A₀
A₁
A₂
A₃
ROW
ADDRESS
A₄
A₅
A₆
A₇
ADDRESS
DECODER
A₈
A₉
A₁₀
COLUMN
A₁₁
ADDRESS
A₁₂
CS
PROGRAM–
MABLE
ARRAY
COLUMN
MULTI–
PLEXER
POWER DOWN
(7C261)
Pin Configurations
O₇
DIP/Flatpack
O₆
Top View
A₇ 1
24 ^VCC
LCC/PLCC (OpaqueOnly)
Top View
A₆ 2
23 ^A8
O₅
A₅ 3
22 A9
O₄
A₄ ⁴
A₃ 5
A₂ 6
A₁ 7
21 ^A10
20 ^CS
19 ^A11
18 ^A12
4 3 2 1 28 27 26
A₄ 5
A₃ 6
A_{2 7}
A_{1 8}
7C261
7C263
25 ^A10
24 CS
23 A11
22 ^A12
O₃
A₀
O₀
8 ^7C261 17 ^O7
9
7C263
7C264 ¹⁶
O₆
O₁ 10
15 ^O5
A_{0 9}
21 NC
NC ₁₀
20 O7
O_{0 11}
19 O₆
12 1314151617 18
O₂
O₂ 11
14 O4
GND ¹²
13 O₃
O₁
O₀
For an 8K x 8 Registered PROM, see theCY7C265.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-04010 Rev. **
Revised March 4, 2002