CY7C2562XV18 Datasheet, PDF (1/27 Pages) Cypress Semiconductor – 72-Mbit QDR® II+ Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

CY7C2562XV18, CY7C2564XV18
72-Mbit QDR^® II+ Xtreme SRAM 2-Word
Burst Architecture (2.5 Cycle Read Latency) with ODT
72-Mbit QDR® II+ Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Features
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 450 MHz clock for high bandwidth
■ 2-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces on both read and write ports
(data transferred at 900 MHz) at 450 MHz
■ Available in 2.5 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ On-Die Termination (ODT) feature
❐ Supported for D_[x:0], BWS_[x:0], and K/K inputs
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR™-II+ Xtreme operates with 2.5 cycle read latency when
DOFF is asserted HIGH
■ Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
■ Available in × 18, and × 36 configurations
■ Full data coherency, providing most current data
■ Core V_DD = 1.8 V ± 0.1 V; V_DDQ = 1.4 V to 1.6 V
❐ Supports 1.5 V I/O supply
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■ CY7C2564XV18 offered in both Pb-free and non Pb-free
packages and CY7C2562XV18 offered in Pb-free package
only.
■ JTAG 1149.1 compatible test access port
■ Phase-locked loop (PLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C2562XV18 – 4 M × 18
CY7C2564XV18 – 2 M × 36
Functional Description
The CY7C2562XV18 and CY7C2564XV18 are 1.8 V
Synchronous Pipelined SRAMs, equipped with QDR™-II+
architecture. Similar to QDR II architecture, QDR II+ architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
dedicated data inputs to support write operations. QDR II+
architecture has separate data inputs and data outputs to
completely eliminate the need to “turnaround” the data bus that
exists with common devices. Access to each port is through a
common address bus. Addresses for read and write addresses
are latched on alternate rising edges of the input (K) clock.
Accesses to the QDR II+ read and write ports are completely
independent of one another. To maximize data throughput, both
read and write ports are equipped with DDR interfaces. Each
address location is associated with two 18-bit words
(CY7C2562XV18), or 36-bit words (CY7C2564XV18) that burst
sequentially into or out of the device. Because data can be
transferred into and out of the device on every rising edge of both
input clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus “turnarounds”.
These devices have an on-die termination (ODT) feature
supported for D_[x:0], BWS_[x:0], and K/K inputs, which helps
eliminate external termination resistors, reduce cost, reduce
board area, and simplify board routing.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
Description
450 MHz 366 MHz Unit
450
366 MHz
× 18 1205
970
mA
× 36 1445
1165
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-70204 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 8, 2012