CY7C245A Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 2K x 8 Reprogrammable Registered PROM

CY7C245A
2K x 8 Reprogrammable Registered PROM
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
— 15-ns address set-up
— 10-ns clock to output
• Low power
— 330 mW (commercial) for -25 ns
— 660 mW (military)
• Programmable synchronous or asynchronous output
enable
• On-chip edge-triggered registers
• Programmable asynchronous register (INIT)
• EPROM technology, 100% programmable
• Slim, 300-mil, 24-pin plastic or hermetic DIP
• 5V ±10% V_CC, commercial and military
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static
discharge
Logic Block Diagram
INIT
A0
A1
A2
A3
ROW
ADDRESS
PROGRAMMABLE
ARRAY
MULTIPLEXER
A4
A5
A6
ADDRESS
DECODER
A7
A8
A₉
COLUMN
ADDRESS
A10
E/E S
CP
PROGRAMMABLE
DQ
MULTIPLEXER
C
Functional Description
The CY7C245A is a high-performance, 2K x 8, electrically
programmable, read-only memory packaged in a slim 300-mil
plastic or hermetic DIP. The ceramic package may be
equipped with an erasure window; when exposed to UV light
the PROM is erased and can then be reprogrammed. The
memory cells utilize proven EPROM floating-gate technology
and byte-wide intelligent programming algorithms.
The CY7C245A replaces bipolar devices and offers the advan-
tages of lower power, reprogrammability, superior perfor-
mance and high programming yield. The EPROM cell requires
only 12.5V for the supervoltage, and low current requirements
allow gang programming. The EPROM cells allow each
memory location to be tested 100%, because each location is
written into, erased, and repeatedly exercised prior to encap-
sulation. Each PROM is also tested for AC performance to
guarantee that after customer programming the product will
meet AC specification limits.
The CY7C245A has an asynchronous initialize function (INIT).
This function acts as a 2049th 8-bit word loaded into the
on-chip register. It is user programmable with any desired
word, or may be used as a PRESET or CLEAR function on the
outputs. INIT is triggered by a low level, not an edge.
8-BIT
EDGE-
TRIGGERED
REGISTER
CP
Pin Configurations
DIP Top View
O
A7 ¹
24 V_CC
7
O
A6 2
A5 ³
23 _A8
22 _A9
A4 4
21 A₁₀
6
O
A3 5
A2 6
20 INIT
19 E/ES
5
O
A1 7
A0 8
18 CP
17 O₇
4
O0 9
16 O6
O
O₁ 10
15 ^O5
3
O2 11
14 O4
O
GND 12
13 O₃
2
LCC/PLCC (Opaque only) Top View
O
1
O
4 3 2 1 282726
A4 5
25 ^A10
0
A_{3 6}
A2 ₇
A1 ₈
24 INIT
23
22
EC/PE_S
A0 9
21 NC
NC
O0
10
20
111213141516171819
O7
O6
Selection Guide
Minimum Address Set-up Time
Maximum Clock to Output
Maximum Operating Current Standard
Commercial
Military
7C245A-15
15
10
120
7C245A-18
18
12
120
120
7C245A-25
25
12
90
120
7C245A-35 Unit
35
ns
15
ns
90
mA
120
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-04007 Rev. *D
Revised November 4, 2003