CY7C199_06 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 32K x 8 Static RAM

CY7C199
Features
• High speed
— 12 ns
• Fast t_DOE
• CMOS for optimum speed/power
• Low active power
— 495 mW (Max, “L” version)
• Low standby power
— 0.275 mW (Max, “L” version)
• 2V data retention (“L” version only)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Available in pb-free 28-pin TSOP I and 28-pin (300-Mil)
Molded DIP
Logic Block Diagram
A₀
A₁
A₂
A₃
A₄
AA₅₆
A₇
A₈
A₉
CE
WE
OE
INPUT BUFFER
32K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
Selection Guide
Maximum Access Time
Maximum Operating Current
L
Maximum CMOS Standby Current
L
32K x 8 Static RAM
Functional Description
The CY7C199 is a high-performance CMOS static RAM
organized as 32,768 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE) and active
LOW Output Enable (OE) and tri-state drivers. This device has
an automatic power-down feature, reducing the power
consumption by 81% when deselected. The CY7C199 is in the
standard 300-mil-wide DIP, SOJ, and LCC packages.
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O₀ through I/O₇) is written into the memory location
addressed by the address present on the address pins (A₀
through A₁₄). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. A die coat is used to improve alpha immunity.
Pin Configurations
DIP
Top View
I/O₀
I/O₁
I/O₂
A₅ 1
A_{6 2}
A₇ 3
A_{8 4}
A_{9 5}
A_{10 6}
A_{11 7}
A_{12 8}
A_{13 9}
A₁₄ 10
I/O₀ 11
I/O₁ 12
I/O₂ 13
GND 14
28 VCC
27 WE
26 A₄
25 A3
24 _A2
23 _A1
22 _OE
21 A₀
20 CE
19 I/O₇
18 I/O₆
17 _I/O5
16 I/O₄
15 I/O₃
I/O₃
I/O₄
I/O₅
I/O₆
I/O₇
OE
22
A₁
23
A₂
24
A₃
25
A₄
26
WE
27
V _CC
28
A₅
1
A₆
2
A7
3
A₈
4
A₉
5
A ₁₀
6
A ₁₁
7
TSOP I
Top View
(not to scale)
21 A ₀
20 _CE
19 I/O ₇
18 I/O 6
17 I/O 5
16 I/O ₄
15 ^I/O 3
14 GND
13 I/O 2
12 I/O 1
11 I/O ₀
10 A 14
9 A ₁₃
8 A ₁₂
–12
–15
–20
Unit
12
15
20
ns
160
155
150
mA
90
10
10
10
mA
0.05
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05160 Rev. *B
Revised August 3, 2006