CY7C199N_11 Datasheet, PDF (1/14 Pages) Cypress Semiconductor – 32 K × 8 Static RAM Automatic power-down when deselected

32 K × 8 Static RAM
Features
■ High speed
❐ 15 ns
■ Fast t_DOE
■ CMOS for optimum speed/power
■ Low active power
❐ 550 mW (max, 15 ns “L” version)
■ Low standby power
❐ 0.275 mW (max, “L” version)
■ 2 V data retention (“L” version only)
■ Easy memory expansion with CE and OE features
■ TTL-compatible inputs and outputs
■ Automatic power-down when deselected
Logic Block Diagram
CY7C199N
32 K × 8 Static RAM
Functional Description
The CY7C199N is a high-performance CMOS static RAM
organized as 32,768 words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE) and active LOW
Output Enable (OE) and three-state drivers. This device has an
automatic power-down feature, reducing the power consumption
by 81% when deselected. The CY7C199NN is in the standard
300-mil-wide DIP, SOJ, and LCC packages.
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O₀ through I/O₇) is written into the memory location addressed
by the address present on the address pins (A₀ through A₁₄).
Reading the device is accomplished by selecting the device and
enabling the outputs, CE and OE active LOW, while WE remains
inactive or HIGH. Under these conditions, the contents of the
location addressed by the information on address pins are
present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable (WE)
is HIGH. A die coat is used to improve alpha immunity.
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CE
WE
OE
INPUT BUFFER
1024 x 32 x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
I/O₆
I/O₇
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-06493 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 29, 2011
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