CY7C199D_09 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 256K (32K x 8) Static RAM

CY7C199D
256K (32K x 8) Static RAM
Features
■ Temperature ranges
❐ Industrial: –40°C to 85°C
❐ Automotive-E: –40°C to 125°C
■ Pin and function compatible with CY7C199C
■ High speed
❐ t_AA = 10 ns (Industrial)
■ Low active power
❐ I_CC = 80 mA at 10 ns
■ Low CMOS standby power
❐ I_SB2 = 3 mA
■ 2.0V Data Retention
■ Automatic power down when deselected
■ CMOS for optimum speed/power
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in Pb-free 28-pin 300-Mil wide Molded SOJ, 28-pin
300-Mil wide SOIC and 28-pin TSOP I packages
Logic Block Diagram
Functional Description
The CY7C199D is a high performance CMOS static RAM
organized as 32,768 words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE) and tri-state drivers. This device has an
automatic power down feature, reducing the power consumption
when deselected. The input and output pins (IO₀ through IO₇)
are placed in a high impedance state when the device is
deselected (CE HIGH), the outputs are disabled (OE HIGH), or
during a write operation (CE LOW and WE LOW).
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight IO pins (IO₀ through IO₇) is
then written into the location specified on the address pins (A₀
through A₁₄).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appears on the IO pins.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
INPUT BUFFER
IO0
A0
IO1
A1
A2
IO2
A3
32K x 8
A4
IO3
A5
ARRAY
A6
IO4
A7
A8
IO5
A9
IO6
CE
WE
COLUMN DECODER
POWER
DOWN
IO7
OE
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05471 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 28, 2009
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