CY7C199B Datasheet, PDF (1/15 Pages) Cypress Semiconductor – 32K x 8 Static RAM

PRELIMINARY
CY7C199B
Features
• High speed
— 10 ns
• Fast t_DOE
• CMOS for optimum speed/power
• Low active power
— 495 mW (max, 10 ns “L” version)
• Low standby power
— 0.275 mW (max, “L” version)
• 2V data retention (“L” version only)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Functional Description
The CY7C199B is a high-performance CMOS static RAM or-
ganized as 32,768 words by 8 bits. Easy memory expansion
32K x 8 Static RAM
is provided by an active LOW Chip Enable (CE) and active
LOW Output Enable (OE) and three-state drivers. This device
has an automatic power-down feature, reducing the power
consumption by 81% when deselected. The CY7C199B is in
the standard 300-mil-wide DIP, SOJ, and LCC packages.
An active LOW Write Enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O₀
through I/O₇) is written into the memory location addressed by
the address present on the address pins (A₀ through A₁₄).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. A die coat is used to improve alpha immunity.
Logic Block Diagram
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
A₉
CE
WE
OE
INPUT BUFFER
1024 x 32 x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (mA)
L
Maximum CMOS
Standby Current (mA) _L
199B-8
8
120
0.5
Shaded area contains advance information.
199B-10
10
110
90
0.5
0.05
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
I/O₆
C199B–1
I/O₇
Pin Configurations
DIP / SOJ / SOIC
Top View
LCC
Top View
A₅ 1
A_{6 2}
A₇ 3
A_{8 4}
A_{9 5}
A_{10 6}
A_{11 7}
A_{12 8}
A_{13 9}
A₁₄ 10
I/O₀ 11
I/O₁ 12
I/O₂ 13
GND 14
28 VCC
27 WE
26 A₄
25 A3
24 _A2
23 _A1
22 _OE
21 A₀
20 CE
19 I/O₇
18 I/O₆
3 2 1 28 27
A₈ 4
26 A₄
A₉ 5
25 A₃
A₁₀ 6
A₁₁ 7
A₁₂ 8
24 A₂
23 A₁
22 OE
A₁₃ 9
A₁₄ 10
21 A₀
20 _CE
I/O₀ 11
19 I/O₇
I/O₁ 12
18 I/O₆
1314151617
17 _I/O5
C199–3
16 I/O₄
15 I/O₃
C199B–2
OE
22
A₁
23
A₂
24
A3
25
A₄
26
WE
27
V _CC
28
A₅
1
A₆
2
A7
3
A₈
4
A₉
5
A ₁₀
6
A ₁₁
7
TSOP I
Top View
(not to scale)
21 A 0
20 CE
19 I/O 7
18 I/O 6
17 I/O 5
16 I/O ₄
15 ^I/O 3
14 GND
13 I/O 2
12 I/O 1
11 I/O 0
10 A 14
9 A 13
8 A ₁₂
C199–4
199B-12
12
160
90
10
0.05
199B-15
15
155
90
10
0.05
199B-20
20
150
90
10
0.05
199B-25
25
150
80
10
0.05
199B-35
35
140
70
10
0.05
199B-45
45
140
10
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
June 13, 2000