CY7C197N Datasheet, PDF (1/7 Pages) Cypress Semiconductor – 256Kx1 Static RAM

Features
• High speed
— 25 ns
• CMOS for optimum speed/power
• Low active power
— 880 mW
• Low standby power
— 220 mW
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Logic Block Diagram
INPUT BUFFER
A₁₃
A₁₄
A₁₅
A₁₆
A₁₇
A₀
1024 x 256
A₁
ARRAY
A₂
A₃
A₄
COLUMN
DECODER
POWER
DOWN
A₅ A₆ A₇ A₈ A₉ A₁₀ A₁₁ A₁₂
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
CY7C197N
256Kx1 Static RAM
Functional Description
The CY7C197N is a high-performance CMOS static RAM
organized as 256K words by 1 bit. Easy memory expansion is
provided by an active LOW Chip Enable (CE) and three-state
drivers. The CY7C197N has an automatic power-down
feature, reducing the power consumption by 75% when
deselected.
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW. Data on the
input pin (D_IN) is written into the memory location specified on
the address pins (A₀ through A₁₇).
Reading the device is accomplished by taking chip enable
(CE) LOW while Write Enable (WE) remains HIGH. Under
these conditions the contents of the memory location specified
on the address pins will appear on the data output (D_OUT) pin.
The output pin stays in a high-impedance state when Chip
Enable (CE) is HIGH or Write Enable (WE) is LOW.
The CY7C197N utilizes a die coat to insure alpha immunity.
DI
DO
CE
WE
Pin Configurations
DIP
Top View
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
D_OUT
WE
GND
1
24
2
23
3
22
4
21
5
20
6 7C197 19
7
18
8
17
9
16
10
15
11
14
12
13
V_CC
A₁₇
A₁₆
A₁₅
A₁₄
A₁₃
A₁₂
A₁₁
A₁₀
A₉
D_IN
CE
-25
-45
25
45
95
30
30
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-06495 Rev. **
Revised February 2, 2006
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