CY7C194B Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 256 Kb (64K x 4) Static RAM

Features
• Fast access time: 12 ns, 15 ns, and 25 ns
• Wide voltage range: 5.0V ± 10% (4.5V to 5.5V)
• CMOS for optimum speed/power
• TTL-compatible inputs and outputs
• Available in 24 DIP, 24 SOJ, 28 DIP, and 28 SOJ
Logic Block Diagram
Input Buffer
CY7C194B
CY7C195B
256 Kb (64K x 4) Static RAM
General Description¹
The CY7C194B-CY7C195B is a high-performance CMOS
Asynchronous SRAM organized as 64K × 4 bits that supports
an asynchronous memory interface. The device features an
automatic power-down feature that significantly reduces
power consumption when deselected. Output enable (OE) is
supported only in CY7C195B.²
See the Truth Table in this data sheet for a complete
description of read and write modes.
The CY7C194B-CY7C195B is available in 24 DIP, 24 SOJ, 28
DIP, and 28 SOJ package(s).
RAM Array
Column Decoder
I/Ox
Power
Down
Circuit
X
CE
WE
OE
(7C195 only)
A
X
Product Portfolio
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Notes:
12 ns
12
90
10
15 ns
15
80
10
25 ns
Unit
25
ns
80
mA
10
mA
1. For best-practice recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. All OE-specific descriptions and parameters in this datasheet pertain to CY7C195 only.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05409 Rev. *A
Revised September 17, 2003