CY7C192_08 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 64K x 4 Static RAM with Separate IO

CY7C192
64K x 4 Static RAM with Separate IO
Features
■ High speed
❐ 15 ns
■ CMOS for optimum speed/power
■ Low active power
❐ 860 mW
■ Low standby power
❐ 55 mW
■ TTL-compatible inputs and outputs
■ Automatic power down when deselected
■ Available in Pb-free and non Pb-free 28-Pin Molded SOJ
package
Functional Description
The CY7C192 is a high performance CMOS static RAM
organized as 65,536 x 4 bits with separate IO. Easy memory
expansion is provided by active LOW Chip Enable (CE) and
tri-state drivers. It has an automatic power down feature that
reduces power consumption by 75% when deselected.
Writing to the device is accomplished when the Chip Enable (CE)
and write enable (WE) inputs are both LOW.
Data on the four input pins (I₀ through I₃) is written into the
memory location specified on the address pins (A₀ through A₁₅).
Reading the device is accomplished by taking the Chip Enable
(CE) LOW while the Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location specified
on the address pins appears on the four data output pins.
The output pins stay in high impedance state when Write Enable
(WE) is LOW or Chip Enable (CE) is HIGH.
A die coat ensures alpha immunity.
Logic Block Diagram
I₀
I₁
I₂
I₃
INPUT BUFFER
AA₁₀
A₂
O₀
A₃
A₄
64K x 4
O₁
A₅
ARRAY
A₆
A₇
O₂
A₈
A₉
O₃
COLUMN
DECODER
POWER
DOWN
CE
WE
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05047 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 15, 2008
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