CY7C192_06 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – 64K x 4 Static RAM with Separate I/O

CY7C192
64K x 4 Static RAM
with Separate I/O
Features
• High speed
— 12 ns
• CMOS for optimum speed/power
• Low active power
— 860 mW
• Low standby power
— 55 mW
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Available in non Pb-free 28-Lead Molded SOJ package.
Functional Description
The CY7C192 is a high-performance CMOS static RAM
organized as 65,536 x 4 bits with separate I/O. Easy memory
expansion is provided by active LOW Chip Enable (CE) and
tri-state drivers. It has an automatic power-down feature,
reducing the power consumption by 75% when deselected.
Writing to the device is accomplished when the Chip Enable
(CE) and write enable (WE) inputs are both LOW.
Data on the four input pins (I₀ through I₃) is written into the
memory location specified on the address pins (A₀ through
A₁₅).
Reading the device is accomplished by taking the Chip Enable
(CE) LOW while the Write Enable (WE) remains HIGH. Under
these conditions the contents of the memory location specified
on the address pins will appear on the four data output pins.
The output pins stay in high-impedance state when Write
Enable (WE) is LOW, or Chip Enable (CE) is HIGH.
A die coat is used to insure alpha immunity.
Logic Block Diagram
INPUT BUFFER
AA₁₀
A₂
A₃
A₄
64K x 4
A₅
ARRAY
A₆
A₇
A₈
A₉
COLUMN
DECODER
POWER
DOWN
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
I₀
I₁
I₂
I₃
O₀
O₁
O₂
O₃
CE
WE
-12
12
155
10
Pin Configurations
SOJ
Top View
A₆ 1
A₇ 2
A₈ 3
A₉ 4
A₁₀ 5
A₁₁ 6
A₁₂ 7
A₁₃ 8
A₁₄ 9
A₁₅ 10
I₀ 11
I₁ 12
CE 13
GND 14
28 ^VCC
27 A5
26 A₄
25 A₃
24 A₂
23 A₁
22 A₀
21 I₃
20 I₂
19 O₃
18 O₂
17 O₁
16 _O0
15 WE
-15
Unit
15
ns
145
mA
10
mA
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05047 Rev. *C
Revised August 3, 2006
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