CY7C185_01 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 8K x 8 Static RAM

185
CY7C185
8K x 8 Static RAM
Features
• High speed
— 15 ns
• Fast t_DOE
• Low active power
— 715 mW
• Low standby power
— 220 mW
• CMOS for optimum speed/power
• Easy memory expansion with CE₁, CE₂, and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Functional Description
The CY7C185 is a high-performance CMOS static RAM orga-
nized as 8192 words by 8 bits. Easy memory expansion is
Logic Block Diagram
INPUT BUFFER
A₁
A₂
A₃
A₄
256 x 32 x 8
A₅
ARRAY
A₆
A₇
A₈
CE₁
CE₂
POWER
COLUMN DECODER ^DOWN
WE
OE
Selection Guide^[1]
7C185–15
Maximum Access Time (ns)
15
Maximum Operating Current (mA)
130
Maximum Standby Current (mA)
40/15
Note:
1. For military specifications, see the CY7C185A data sheet.
provided by an active LOW chip enable (CE₁), an active HIGH
chip enable (CE₂), and active LOW output enable (OE) and
three-state drivers. This device has an automatic power-down
feature (CE₁ or CE₂), reducing the power consumption by 70%
when deselected. The CY7C185 is in a standard 300-mil-wide
DIP, SOJ, or SOIC package.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE₁ and WE in-
puts are both LOW and CE₂ is HIGH, data on the eight data
input/output pins (I/O₀ through I/O₇) is written into the memory
location addressed by the address present on the address
pins (A₀ through A₁₂). Reading the device is accomplished by
selecting the device and enabling the outputs, CE₁ and OE
active LOW, CE₂ active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location ad-
dressed by the information on address pins are present on the
eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
Pin Configurations
DIP/SOJ/SOIC
Top View
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
NC ₁
A_{4 2}
A_{5 3}
A_{6 4}
A_{7 5}
A_{8 6}
A_{9 7}
A_{10 8}
A_{11 9}
A_{12 10}
I/O_{0 11}
I/O_{1 12}
I/O_{2 13}
GND ₁₄
28 ^VCC
27 ^WE
26 ^CE2
25 ^A3
24 ^A2
23 ^A1
22 ^OE
21 ^A0
20 ^CE1
19 ^I/O7
18 ^I/O6
17 ^I/O5
16 ^I/O4
15 ^I/O3
C185–2
I/O₅
I/O₆
I/O₇
C185–1
7C185–20
20
110
20/15
7C185–25
25
100
20/15
7C185–35
35
100
20/15
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05043 Rev. **
Revised August 24, 2001