CY7C182_01 Datasheet, PDF (1/7 Pages) Cypress Semiconductor – 8Kx9 Static RAM

182
CY7C182
Features
• High speed
— t_AA = 25 ns
• x9 organization is ideal for cache memory applications
• CMOS for optimum speed/power
• Low active power
— 770 mW
• Low standby power
— 195 mW
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Easy memory expansion with CE₁, CE₂, OE options
Functional Description
The CY7C182 is a high-speed CMOS static RAM organized
as 8,192 by 9 bits and it is manufactured using Cypress’s high-
performance CMOS technology. Access times as fast as 25 ns
are available with maximum power consumption of only 770
mW.
8Kx9 Static RAM
The CY7C182, which is oriented toward cache memory appli-
cations, features fully static operation requiring no external
clocks or timing strobes. The automatic power-down feature
reduces the power consumption by more than 70% when the
circuit is deselected. Easy memory expansion is provided by
an active-LOW Chip Enable (CE₁), an active HIGH Chip En-
able (CE₂), an active-LOW Output Enable (OE), and three-
state drivers.
An active-LOW Write Enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE₁ and WE in-
puts are both LOW, data on the nine data input/output pins
(I/O₀ through I/O₈) is written into the memory location ad-
dressed by the address present on the address pins (A₀
through A₁₂). Reading the device is accomplished by selecting
the device and enabling the outputs, (CE₁ and OE active LOW
and CE₂ active HIGH), while (WE) remains inactive or HIGH.
Under these conditions, the contents of the location addressed
by the information on address pins is present on the nine data
input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configuration
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
CE₁
CE2
WE
OE
INPUT BUFFER
256 x 32 x 9
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
I/O₆
I/O₇
I/O₈
C182–1
DIP/SOJ
Top View
A_{4 1}
A_{5 2}
A₆ 3
A₇ 4
A₈ 5
A_{9 6}
A_{10 7}
A_{11 8}
A_{12 9}
I/O ₀ 10
I/O ₁ 11
I/O ₂ 12
I/O ₃ 13
GND 14
28 ^VCC
27 ^WE
26 CE 2
25 A3
24 A2
23 ^A1
22 ^OE
21 ^A0
20 ^CE 1
19 I/O 8
18 I/O 7
17 I/O 6
16 I/O 5
15 I/O 4
C182–2
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
7C182-25
25
140
35
7C182-35
35
140
35
7C182-45
45
140
35
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05031 Rev. **
Revised August 24, 2001