CY7C1561KV18 Datasheet, PDF (1/28 Pages) Cypress Semiconductor – 72-Mbit QDR-II+ SRAM 4-Word Burst Architecture

CY7C1561KV18, CY7C1576KV18
PRELIMINARY CY7C1563KV18, CY7C1565KV18
72-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency)
Features
Configurations
■ Separate Independent Read and Write Data Ports
❐ Supports concurrent transactions
■ 550 MHz Clock for High Bandwidth
■ 4-word Burst for Reducing Address Bus Frequency
■ Double Data Rate (DDR) Interfaces on both Read and Write
Ports (data transferred at 1100 MHz) at 550 MHz
■ Available in 2.5 Clock Cycle Latency
■ Two Input Clocks (K and K) for precise DDR Timing
❐ SRAM uses rising edges only
■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
■ Data Valid Pin (QVLD) to indicate Valid Data on the Output
■ Single Multiplexed Address Input Bus latches Address Inputs
for Read and Write Ports
■ Separate Port selects for Depth Expansion
■ Synchronous Internally Self-timed Writes
■ QDR™-II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to QDR-I Device with one Cycle Read Latency
when DOFF is asserted LOW
■ Available in x8, x9, x18, and x36 Configurations
■ Full Data Coherency, providing Most Current Data
■ Core V_DD = 1.8V± 0.1V; I/O V_DDQ = 1.4V to V_DD ^[1]
❐ Supports both 1.5V and 1.8V I/O supply
■ HSTL Inputs and Variable Drive HSTL Output Buffers
■ Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free Packages
■ JTAG 1149.1 compatible Test Access Port
■ Phase-Locked Loop (PLL) for Accurate Data Placement
With Read Cycle Latency of 2.5 cycles:
CY7C1561KV18 – 8M x 8
CY7C1576KV18 – 8M x 9
CY7C1563KV18 – 4M x 18
CY7C1565KV18 – 2M x 36
Functional Description
The CY7C1561KV18, CY7C1576KV18, CY7C1563KV18, and
CY7C1565KV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II+ architecture. Similar to QDR-II archi-
tecture, QDR-II+ architecture consists of two separate ports: the
read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR-II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turnaround” the
data bus that exists with common I/O devices. Each port is
accessed through a common address bus. Addresses for read
and write addresses are latched on alternate rising edges of the
input (K) clock. Accesses to the QDR-II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 8-bit
words (CY7C1561KV18), 9-bit words (CY7C1576KV18), 18-bit
words (CY7C1563KV18), or 36-bit words (CY7C1565KV18) that
burst sequentially into or out of the device. Because data is trans-
ferred into and out of the device on every rising edge of both input
clocks (K and K), memory bandwidth is maximized while simpli-
fying system design by eliminating bus “turnarounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Table 1. Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
550 MHz
550
x8
900
500 MHz
500
830
450 MHz
450
760
400 MHz
400
690
Unit
MHz
mA
x9
900
830
760
690
x18
920
850
780
710
x36
1310
1210
1100
1000
Note
1. The Cypress QDR-II+ devices surpass the QDR consortium specification and can support V_DDQ = 1.4V to V_DD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-15878 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 03, 2009
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