CY7C1512 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – 64K x 8 Static RAM

1CY 7C15 12
PRELIMINARY
CY7C1512
64K x 8 Static RAM
Features
• High speed
— t_AA = 15 ns
• CMOS for optimum speed/power
• Low active power
— 770 mW
• Low standby power
— 28 mW
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE₁, CE₂, and OE options
Functional Description
The CY7C1512 is a high-performance CMOS static RAM or-
ganized as 65,536 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE₁), an active
HIGH chip enable (CE₂), an active LOW output enable (OE),
and three-state drivers. This device has an automatic pow-
er-down feature that reduces power consumption by more
than 75% when deselected.
Writing to the device is accomplished by taking chip enable
one (CE₁) and write enable (WE) inputs LOW and chip enable
two (CE₂) input HIGH. Data on the eight I/O pins (I/O₀ through
I/O₇) is then written into the location specified on the address
pins (A₀ through A₁₅).
Reading from the device is accomplished by taking chip en-
able one (CE₁) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE₂) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE₁
HIGH or CE₂ LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE₁ LOW, CE₂ HIGH, and WE LOW).
The CY7C1512 is available in standard TSOP type I and
450-mil-wide plastic SOIC packages.
Logic Block Diagram
Pin Configurations
SOIC
Top View
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
CE₁
CE₂
WE
OE
INPUT BUFFER
64K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O₀
I/O₁
I/O₂
I/O₃ A11
1
A₉
2
I/O₄
A₈
A₁₃
3
4
WE
5
I/O₅
CE₂
A₁₅
6
7
V_CC
8
I/O₆
NC
NC
9
10
A₁₄
11
A₁₂
12
I/O₇ A₇
13
A₆
14
1512-1
A₅
15
A₄
16
NC 1
NC ₂
A₁₄ 3
A₁₂ 4
A₇ 5
A₆ 6
A_{5 7}
A₄ 8
A₃ 9
A₂ 10
A_{1 11}
A₀ 12
I/O_{0 13}
I/O_{1 14}
I/O_{2 15}
GND ₁₆
32 VCC
31 A₁₅
30 CE₂
29 WE
28 _A13
27 _A8
26 _A9
25 _A11
24 _OE
23 A₁₀
22 CE₁
21 I/O7
20 ^I/O6
19 ^I/O5
18 ^I/O4
17 I/O3
TSOP I
Top View
(not to scale)
1512-2
32 OE
31
A₁₀
30 CE₁
29 I/O₇
28 I/O₆
27 I/O₅
26 I/O₄
25 I/O₃
24 GND
23 I/O₂
22 I/O₁
21 I/O₀
20 A₀
19 A1
18 A₂
17 A₃
Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Commercial
Maximum CMOS
Standby Current (mA)
Commercial
7C1512-15
15
140
5
7C1512-20
20
130
5
7C1512-25
25
120
5
7C1512-35
35
110
5
7C1512-70
70
110
5
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
June 1996 – Revised October 1996