CY7C150_03 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 1Kx4 Static RAM

50
CY7C150
Features
• Memory reset function
• 1024 x 4 static RAM for control store in high-speed com-
puters
• CMOS for optimum speed/power
• High speed
— 10 ns (commercial)
— 12 ns (military)
• Low power
— 495 mW (commercial)
— 550 mW (military)
• Separate inputs and outputs
• 5-volt power supply ±10% tolerance in both commercial
and military
• Capable of withstanding greater than 2001V static dis-
charge
• TTL-compatible inputs and outputs
Functional Description
The CY7C150 is a high-performance CMOS static RAM de-
signed for use in cache memory, high-speed graphics, and
data-acquisition applications. The CY7C150 has a memory re-
set feature that allows the entire memory to be reset in two
memory cycles.
1Kx4 Static RAM
Separate I/O paths eliminates the need to multiplex data in
and data out, providing for simpler board layout and faster sys-
tem performance. Outputs are three-stated during write, reset,
deselect, or when output enable (OE) is held HIGH, allowing
for easy memory expansion.
Reset is initiated by selecting the device (CS = LOW) and tak-
ing the reset (RS) input LOW. Within two memory cycles all
bits are internally cleared to zero. Since chip select must be
LOW for the device to be reset, a global reset signal can be
employed, with only selected devices being cleared at any giv-
en time.
Writing to the device is accomplished when the chip select
(CS) and write enable (WE) inputs are both LOW. Data on the
four data inputs (D₀−D₃) is written into the memory location
specified on the address pins (A₀ through A₉).
Reading the device is accomplished by taking chip select (CS)
and output enable (OE) LOW while write enable (WE) remains
HIGH. Under these conditions, the contents of the memory
location specified on the address pins will appear on the four
output pins (O₀ through O₃).
The output pins remain in high-impedance state when chip
enable (CE) or output enable (OE) is HIGH, or write enable
(WE) or reset (RS) is LOW.
A die coat is used to insure alpha immunity.
Logic Block Diagram
D₀ D₁ D₂ D₃
DATAINPUT
CONTROL
A₀
A₁
A₂
64 x 64
A₃
ARRAY
A₄
A₅
COL^CUM^ON^LD^UEC^MO^NDER
DECODER
RS
CS
OE
WE
O₀
O₁
O₂
O₃
C150–1
Pin Configuration
A3
A4
A5
A6
A7
A8
A9
D0
D1
O0
O1
GND
DIP/SOIC
Top View
1
24
2
23
3
22
4
21
5
20
6 ^{7C150 19}
7
18
8
17
9
16
10
15
11
14
12
13
VCC
A2
A1
A0
RS
CS
WE
OE
D3
D2
O3
O2
C150-2
A₆ A₇ A₈ A₉
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Commercial
Military
Commercial
Military
7C150−10
10
90
7C150−12
12
12
90
100
7C150−15
15
15
90
100
7C150−25
25
25
90
100
7C150−35
35
90
100
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05024 Rev. *A
Revised January 18, 2003